On-chip clock synthesis is performed by the high-frequency phase-locked loop on the S3017 transmitter chip allowing the use of a slower external transmit clock reference. Clock recovery is performed on the S3018 receiver chip by synchronizing its on-chip VCO directly to the incoming data stream. The S3018 also performs SONET/SDH frame detection. The chipset can be used with a 19.44 or 77.76 MHz reference clock, in support of existing system clocking schemes.
The low jitter PECL interface guarantees compliance with the bit-error
rate requirements of the Bellcore, ANSI, and ITU-T standards. The S3017
and S3018 are packaged in a compact 52 PQFP, offering designers a small
package outline.
| Input | Output | |
|---|---|---|
| Throughput | 622.08 Mbps | 622.08 MBaud |
| # bits | 8 | 1 (differential) |
| Frequency | 77.76 MHz | |
| Signal levels | TTL + PECL for clock | PECL |
| Synchronous/sync with idles/asynchronous | synchronous |
| Input data needs coding | yes |
| Error detection | no |
| Power consumption | 890 mW |
| Power supply voltage | +5 V |
| Package size | 52-pin PQFP TEP / 1.44 cm2 /
12.0 x 12.0 x 9.2 mm (with heatsink) |
| Technology | |
| Radiation hardness | unknown |
| Price |
The chip is not providing any coding of the data, so you have to make sure that the datastream has a DC balance and enough transitions to keep the receiver happy. For the latter, it is specified that the receiver will declare loss of signal if it has not detected any transitions within 96 bit times. However, the receiver is specified on a datastream with a minimum transition density of 20%. The outputs from the chip can drive an optical module, but one should make sure there is enough DC balance in the datastream.
The receiving S3018 will be able to detect byte boundaries on the pattern A1h A1h A1h A2h A2h A2h. This pattern recognition may be disabled.
The part is very sensitive to board layout and decoupling. The application note when describing the two PLL loop filter pins reads: "These pins are called out as CAP1 and CAP2. These connections control the internal VCO and are sensitive to coupled noise at the nanovolt level".
CERN - High Speed Interconnect
Erik Van der Bij - 26 January
1998 - Disclaimer