Eight bits of user data or protocol information are loaded into the HOTLink transmitter and are encoded. Serial data is shifted out of the three differential positive ECL (PECL) serial ports at the bit rate (which is 10 times the byte rate).
The HOTLink receiver accepts the serial bit stream at its differential line receiver inputs and, using a completely integrated PLL Clock Synchronizer, recovers the timing information necessary for data reconstruction. The bit stream is deserialized, decoded, and checked for transmission errors. Recovered bytes are presented in parallel to the receiving host along with a byte rate clock.
The 8B/10B encoder/decoder can be disabled in systems that already encode
or scramble the transmitted data. I/O signals are available to create a
seamless interface with both asynchronous FIFOs (i.e., CY7C42X) and clocked
FIFOs (i.e., CY7C44X). A Built-In Self-Test pattern generator and checker
allows testing of the transmitter, receiver, and the connecting link as
a part of a system diagnostic check.
Input | Output | |
---|---|---|
Throughput | 120-320 Mbps (8-bits mode) | 150-400 MBaud |
# bits | 8 or 10 | 1 (single-ended and differential) + 2 redundant |
Frequency | 15-40 MHz | |
Signal levels | TTL and CMOS | 600 mV p-p |
Synchronous/sync with idles/asynchronous | synchronous |
Input data needs coding | no |
Error detection | yes |
Power consumption | 300 mW (1 output used) |
Power supply voltage | +5 V |
Package size | 28-pin PLCC / 1.54 cm2 / 12.4 x 12.4 x 4 mm |
Technology | BiCMOS 0.8 u |
Radiation hardness | unknown |
Price |
The CY7B923 has three differential outputs. Some may be disabled to reduce power consumption and noise generation. The outputs may drive directly a cable, although the application notes recommend some form of common mode suppression on the transmitter side, where they prefer a transformer-based coupling. Transformer-based coupling may be difficult to use in LHC applications where a large magnetic field may exist. Running at 400 Mbps, cable lengths between 50 and 70 m should be feasible, while by passive equaliser circuits the double of this can be reached. Application notes exist that describe those issues in detail.
The CY7B923 can take 8-bit data and will perform 8B10B coding on the data which will give a correct DC balance. The 8B10B coding also introduces some form of error detection. Whenever no data is given to the chip, it will send synchronisation characters K28.5. On the receiving side those characters (except the last one) will be removed. The chip can be used as a simple serialiser, but in this case the byte synchronisation can be difficult to implement. The chip has a relaxed setup time of 5 ns with no hold time requirement. The HOTLink has a built-in self-test which can be started by asserting one pin.
TEMIC Semiconductor sells the TSS923(E)/933(E) chips, which are pin and package compatible to the HOTLink. Those chips are radiation tolerant, covered by the ESA MCRT capability approval domain. On the other hand it only allows a byte clock of 33 MHz maximum, which probably makes it unusable for LHC applications. On the other hand one may ask TEMIC what happens if the chip is used in a controlled environment (temperature and power supply). This radiation tolerant version has the following features:
CERN - High Speed Interconnect
Erik Van der Bij - 4 January
1999 - Disclaimer