Other features such as a sync detector output, a sync detector disable input, and a lock detect output are also provided. The X 9 + X 4 + 1 scrambler and NRZ to NRZI converter may be bypassed to allow the output of the parallel to serial converter to be directly routed to the output drivers. The GS9002 provides pseudo-ECL outputs for the serial data and serial clock as well as a single-ended pseudo-ECL output of the regenerated parallel clock.
The GS9002 directly interfaces with cable drivers GS9007, GS9008 and
GS9009. The device requires a single +5 volt or -5 volt supply and typically
consumes 713 mW of power while driving 100 Ohm loads. The 44 pin PLCC packaging
assures a small footprint for the complete encoder function.
The GS9002 is a monolithic bipolar integrated circuit designed to serialize SMPTE 125M and SMPTE 244M bit parallel digital signals as well as other 8 or 10 bit parallel formats. This device performs the functions of sync detection, parallel to serial conversion, data scrambling (using the X9 + X4 + 1 algorithm), 10x parallel clock multiplication and conversion of NRZ to NRZI serial data. The data rate is automatically set for SMPTE 259M data rates to over 360 Mb/s. Other features include a lock detect output and an internal cable driver capable of driving two 75 Ohm loads.
The GS9002 provides pseudo-ECL outputs for the serial data and serial clock as well as single-ended pseudo-ECL output of the regenerated parallel clock.
The GS9002 directly interfaces with cable drivrs GS9007, GS9008 and GS9009. The device requires a single +5 volt or -5 volt supply and typically consumes 713 mW of power while driving 100 Ohm loads. The 44 pin PLCC packaging assures a small footprint for the complete encoder function.
| Input | Output | |
|---|---|---|
| Throughput | 100-400 Mbps | |
| # bits | 8 or 10 | 1 (differential) + serial clock (differential) |
| Frequency | 10-40 MHz | 100-400 MHz |
| Signal levels | TTL and CMOS | PECL differential |
| Synchronous/asynchronous/sync with idles | synchronous |
| Input data needs coding | no |
| Error detection | no |
| Power consumption | 710 mW |
| Power supply voltage | +5 V |
| Package size | 44-pin PLCC |
| Technology | Bipolar |
| Radiation hardness | unknown |
| Price |
The input of the GS9002 uses the SMPTE-standardised Bit-Parallel Digital Interface, which may be up to 40 MHz, which matches the LHC global clock. Care has to be taken that the chip has an hold time requirement of minimum 3 ns. The setup time is also 3 ns minimum.
The input data can be given directly, as the chip itself is performing the coding. The only thing to watch out is that there are some reserved words. These reserved words are used by the receiver to make the byte synchronisation. In 10-bits mode these words are 0000-0003 and 3FC-3FF in the 10-bit mode and 00 and FF in the 8-bit mode. One can disable this sync detect feature on the GS9002, but probably you will have troubles doing your manual sync detection on the receiver side. I believe that the some of the sync words are filtered out by the receiver chips (GS9005/GS9000 combination).
There are easy-to-use crossbar switch components available that can be used in for applications requiring redundancy.
CERN - High Speed Interconnect
Erik Van der Bij - 20 January
1998 - Disclaimer