From the user’s viewpoint, these products can be thought of as providing a “virtual ribbon cable” interface for the transmission of data. Parallel data (a frame) loaded into the Tx (transmitter) chip is delivered to the Rx (receiver) chip over a serial channel, which can be either a coaxial copper cable or optical link, and is reconstructed into its original parallel form.

The chip set hides from the user all the complexity of encoding, multiplexing, clock extraction, demultiplexing and decoding. Unlike other links, the phase-locked-loop clock extraction circuit also transparently provides for frame synchronization–the user is not troubled with the periodic insertion of frame synchronization words. In addition, the DC balance of the line code is automatically maintained by the chip set. Thus, the user can transmit arbitrary data without restriction. The Rx chip also includes a  state-machine controller (SMC) that provides a startup handshake protocol for the duplex link configuration.

The serial data rate of the Tx/Rx link is selectable in four ranges, and extends from 120 Mbits/s up to 1.25 Gbits/s. This translates into an encoded serial rate of 150-1500 MBaud. The parallel data interface is 16 or 20 bit TTL, pin selectable. A flag bit is available and can be used as an extra 17th or 21st bit under the user’s control. The flag bit can also be used as an even or odd frame indicator for dual-frame transmission. If not used, the link performs expanded error detection.

The serial link is synchronous, and both frame synchronization and bit synchronization are maintained. When data is not available to send, the link maintains synchronization
by transmitting fill frames. Two (training) fill frames are reserved for handshaking during link startup. User control space is also supported. If Control Available (CAV) is asserted at the Tx chip, the least significant 14 or 18 bits of the data are sent and the Rx Control Available (CAV) line will indicate the data as a Control Word.

INTERFACING

The chip has built in differential output drivers. In standard applications a single output is used to drive a 50 Ohm coaxial cable, but the outputs can also be used to drive two differential cables. The datasheet does not describe the maximum length that one can reach. The matching receiver chip (HDMP-1024) has one pair of inputs that has a built in equaliser circuit which can improve the link distance and bit error rate. There is no DC component on the outputs.

Care has to be taken that the chip has an hold time requirement of minimum 2 ns. The setup time is also 2 ns minimum. The chip has a nice feature with which it is easy to multiplex 32-bit data downto two 16-bit datawords that are transferred and back into 32-bits words at the receiver.

The input data can be given directly, as the chip itself is performing the coding. Also the synchronisation of the link is done automatically by the chip. For unidirectional lines some special trick has to be performed to synchronise the link on the Rx chip. The recipe that HP prescribes uses a trick with the LoopBack input to frequency synchronise first on a local crystal and then switches to the normal input connected to the transmitter to make the phase synchronisation. The time it takes to synchronise can vary and is dependent on the match between the clock frequency on the Tx and the Rx. The system only will work if the frequencies are not the same. HP recommends a match in the range between 0.1% and 0.001% (and not outside this range).

The HDMP-1022 has two pairs of outputs which may be used for applications requiring redundancy.

RADIATION HARDNESS

• No data available.
• Chip is built in Bipolar process.
• Package is made from aluminium

OTHER

• select Rx Clk frequency slightly different than the LHC clock

• transmission of 32-bit@40 MHz (1600 Mbaud) is outside guaranteed range
• rate of 1600 Mbaud is too high for normal optical modules
• synchronisation time variable
• hold time of 2 ns
• high power consumption (1.9 Watt)
• radiation hardness unknown with aluminium package

• HDMP-1022/1024 Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os

• HDMP-1012/1014 Low Cost Gigabit Rate Transmit/Receive Chip Set with ECL I/Os (abosolete component)
• HP High-speed I/O comparison
• HDMP-132/1034 new, lower power product, still to be released (March 1999)

• Bernard Dinkespiler in a collaboration of KTH, SMU, ISN and CPPM from the ATLAS Liquid Argon Detector, will build a test board with the HDMP-1022/1024 with VcSEL and test this with a parallel bit error rate tester. In June 1998 they will test this under radiation.
• The predecessor, the HDMP-1012 which has ECL I/O has been used extensively and also radiation measurements have been made. It is unknown if features such as radiation hardness or reliability of the 1012 are also valid for the 1022. Latch-up and unreliability of the HDMP-1012 have been reported, but should be verified.
• Jan-1998. In the ATLAS Level-1 Calorimeter Trigger Processor they used in 1997 the HDMP-1012 (the old G-LINK with ECL I/O) over a 5 meter coax. The G-LINK dropped out when it ran at 1.6 Gbps, but worked fine at 800 Mbps. They think the cause is that the VME power is not clean enough.
• March-1999. In the S-LINK project a Link Source Card and Link Destination Card have been designed using the HDMP-1022/1024. Those cards will be used in radiation tests and by the CMS ECAL project.

• ATLAS LArg - Bernard Dinkespiler
• ATLAS Level-1 Calorimeter Trigger (HDMP-1012 only) - Eric Eisenhandler
• S-LINK - Erik van der Bij
• Hewlett Packard

CERN - High Speed Interconnect
Erik Van der Bij - 4 March 1999 - Disclaimer