INFN MATCH Serialiser
MANUFACTURER'S DEVICE DESCRIPTION
The Match chip is a fully asynchronous electrical parallel to serial to
parallel transceiver using Manchester encoding operating at rates of up
to 1 GHz. Data are sent as 40 bit frames with 32 bit net data, the chip
protocol is fully asynchronous. There is error detection. The chip itself
foresees no flow control. The chip is implemented in GaAs is rad hard (several
Mrad).
TRANSMITTER FEATURES
|
Input |
Output |
| Throughput |
1 Gbps |
2 GBaud (1 GHz) |
| # bits |
32 |
|
| Frequency |
|
|
| Signal levels |
|
|
| Synchronous/asynchronous/sync with idles |
asynchronous |
| Input data needs coding |
no |
| Error detection |
no |
| Power consumption |
|
| Power supply voltage |
+5 V |
| Package size |
|
| Technology |
GaAs |
| Radiation hardness |
several Mrad |
| Price |
|
DESCRIPTION
INTERFACING
The INFN MATCH chip is a serialiser component that is specially designed
for High Energy Physics applications. Unfortunately at this moment not
a lot of information is known. Samples have been produced, but datasheets
are not available.
The input data can be given directly, as the chip itself is performing
the coding.
RADIATION HARDNESS
The chip would be radiation hard as it is built with GaAs technology. However,
no radiation measurements have been done.
OTHER
Not sure if chip will be available from industry.
ISSUES FOR LHC APPLICATIONS
-
no documentation available
-
availability
-
power consumption
-
asynchronous behaviour
-
radiation hardness unknown
DOCUMENTATATION
RELATED COMPONENTS
USERS
-
No known users in High Energy Physics
CONTACT
CERN - High Speed Interconnect
Erik Van der Bij - 21 January
1998 - Disclaimer