This serial link can be used to establish multi–point or point–to–point connections. A unique differential cutoff driver switches from a standard PECL V OH level to cutoff. In the cutoff state the outputs present a high impedance which is required to implement a true shared bus. The part features a 32–bit wide parallel TTL compatible I/O interface that can connect directly with standard memory or bus transceiver devices. The control pins are all TTL compatible to simplify interfacing requirements.
The serial interface is PECL (Positive Emitter Coupled Logic) which provides excellent transmission line drive capability. Because the serial bus is implemented using differential ECL technology, the receiver circuitry exhibits excellent common mode noise rejection.
Input | Output | |
---|---|---|
Throughput | -800 Mbps | 900 Mbaud |
# bits | 32 | 1 differential |
Frequency | 25 MHz | |
Signal levels | TTL | PECL |
Synchronous/sync with idles/asynchronous | synchronous with idles |
Input data needs coding | no |
Error detection | no |
Power consumption | 3500 mW |
Power supply voltage | +5 V |
Package size | 64-pin CQFP 1.44cm2 / 12.0 x 12.0 x 4.0 mm |
Technology | Silicon Bipolar (MOSAIC V) |
Radiation hardness | unknown |
Price | CHF 350 |
The chip has built in differential output drivers. In standard applications a single output is used to drive a 50 Ohm coaxial cable that may be up to 10 m length.There is a DC component on the outputs as no encoding is performed.
Care has to be taken that the chip has a hold time requirement.
In the datasheets Motorola speaks about higher speed versions of the components, but in the last few months (April 1998) web pages with extended descriptions and slideshows have been removed.
CERN - High Speed Interconnect
Erik Van der Bij - 14 April
1998 - Disclaimer