When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected by way of the clock select (CLKSEL) terminal. The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.
The SN75LVDS83 requires no external components and little or no control.
The data bus appears the same at the input to the transmitter and output
of the receiver with the data transmission transparent to the user. The
only user intervention is the possible use of the shutdown/clear (SHTDN)
active-low input to inhibit the clock and shut off the LVDS output drivers
for lower power consumption. A low-level signal on SHTDN clears all internal
registers to a low level.
The SN75LVDS83 is characterized for operation over free-air temperature
ranges of 0 oC to 70 oC.
| Input | Output | |
|---|---|---|
| Throughput | 868-1904 Mbps | 4 * 217 - 476 MBaud +
1 * 62 - 136 MBaud |
| # bits | 28 | 5 |
| Frequency | 31-68 MHz | |
| Signal levels | LV-TTL, 5 Volt Tolerant | LVDS differential |
| Synchronous/sync with idles/asynchronous | synchronous |
| Input data needs coding | no |
| Error detection | no |
| Power consumption | 250 mW, 1 mW when disabled |
| Power supply voltage | +3.3 V |
| Package size | 56-pin TSSOP with 20-MIL terminal pitch /
1.12 cm2 / 14 x 8 x 1.2 mm |
| Technology | BiCMOS, minimum feature size 0.6 micron, the Ft of the bipolar is about 13Ghz |
| Radiation hardness | unknown |
| Price |
The inputs of the FLATLINK chips are Low Voltage TTL, and are 5 Volt tolerant. A nice feature of the 75LVDS83 is that you may select whether the data will be sampled at the positive or the negative edge of the clock. The chip needs a hold time of 1.5 ns, and a setup time of 3 ns. The chip transfers the data completely transparently, no precautions have to be taken to synchronise the link. No coding is performed, which means that the lines may have a DC-component; this might be a problem if sending data over an optical link.
The electrical outputs of the FLATLINK chips are normally used to drive
the short cable from the bottom part of a laptop PC to the top part. In
examples TI speaks about 20 cm and 50 cm cables. National Semiconductor
describes a 2 m system in their LVDS
Owner's Manual. Much longer lengths are probably not possible because
of jitter and skew. The main problem of the approach of sending the clock
signal over a seperate line than the data is the maxim allowed skew between
the lines. TI has a few application notes that describe the skew issues
in detail. Roughly only 290 ps of skew is allowed for the components between
the transmitter and the receiver. This might be difficult to reach if we
would send the data over a long parallel optical fibre.
The same type of chip is available in many variations: 18-bit, 21-bit,
24-bit and 28-bit. Also National Semiconductor has similar chips.
CERN - High Speed Interconnect
Erik Van der Bij - 23 January
1998 - Disclaimer