| Input | Output | |
|---|---|---|
| Throughput | 850 Mbps | 1062.5 Mbaud |
| # bits | 20 | 1 (differential) |
| Frequency | 53.125 MHz | |
| Signal levels | TTL | PECL |
| Synchronous/sync with idles/asynchronous | synchronous with idles |
| Input data needs coding | yes: 8B10B with comma character for synchronisation |
| Error detection | no |
| Power consumption | 1000 mW |
| Power supply voltage | +3.3 V |
| Package size | 52-pin PQFP / 1.74 cm2 / 13.2x13.2x2 mm |
| Technology | |
| Radiation hardness | unknown |
| Price |
The input of the VSC7115 should be 8B10B coded data, for which you may buy special chips such as the VSC7107. It is possible to implement the 8B10B coding circuit yourself; several projects at CERN have done this. The major problem for applications for the LHC experiment is that the input frequency should be exactly 53.125 MHz and not the 40 MHz that is commonly used in LHC. This is due to the Phase Locked Loop circuitry in the VSC7115 that is optimised for Fibre Channel applications. Also it is necessary to send from time to time the Fibre Channel 'comma' character which is used to synchronise the link.
Other Fibre Channel and Gigabit Ethernet transceivers exist, but they have similar limitations.
CERN - High Speed Interconnect
Erik Van der Bij - 22 January
1998 - Disclaimer