Application of T9000 to CPLEAR
The T9000 has several improvements over previous generations of Transputers in both performance and functionality. Improved performance has been gained through an increase in clock speed (50 MHz design), the implementation of an on-chip cache, and a pipelined superscalar architecture.
Improved communication is provided by the new Data/Strobe (DS) link technology which currently operates at 100 Mbits/s. Messages are divided into a sequence of packets, each of which has the structure shown in Fig. 2. All routing information is contained in the packet header. The T9000 implements a maximum packet body of 32 bytes. Any device receiving a data packet replies to the sender with an acknowledge packet. No further packets are transmitted by the sender until the corresponding acknowledge has been received by the sender.
Communication between T9000 processes is performed via virtual links. A virtual link is a single logical communication connection between two processes mapped onto a physical processor link. The VCP of the T9000 is a hardware communications processor which multiplexes the virtual links onto a specified physical processor link. Packets from separate virtual links are interleaved onto the physical link, allowing separate processes to communicate simultaneously. The virtual link to which the packet is being sent is contained in the packet header.
T9000 processors can be directly connected using their DS links or connected to a network of C104 packet routing chips, thus allowing the construction of large networks with scalable communication bandwidth between nodes. In the latter case, additional packet headers are required to route the packet through the switching network.
Two separate control links allow the T9000 to be controlled (processor initialization and loading) and monitored for errors, even when there are faults in the normal communications network. These control links may be daisy chained and/or connected via C104 packet routers.
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