Effective exploitation of multiple processors in a distributed computing environment relies on a low latency, high bandwidth, inter-processor communication network. The IEEE 1355 HS-Link technology allows such networks to be constructed. It can potentially also be applied in other applications which require high performance switching, such as LAN or WAN routers, ATM switches, or high performance data acquisition systems. We present initial experience with HS-Links and the associated silicon implementations. A 64 node HS-Link switching network based on these devices is currently being constructed at CERN. We report on the overall architecture of this network testbed and the design of the individual components.
The work presented here has been carried out within the framework of the European
Union's ESPRIT
program as part of the OMI Macramé and ARCHES projects.