GSN to S-LINK
FIFO
FIFO
FPGA
TO BRIDGE
PATRIOTPROCESSOR
RJ 12
RS232
Register
SET-UP
FIFO
FIFO
FIFO
FIFO
FROM BRIDGE
FPGA
reset
Control etc
Glue Logic
Synchronization etc.
16 bit 66 MHz 132 MB/s
64 bit
40 MHz
320 MB/s
64 bit
40 MHz
320 MB/s
PROCESSOR BUS
FPGA
FPGA
Version with 6 S-LINK CANNELS
Added Bandwidth 100 Mbyte/s per Interface
Total Added bandwidth 800 Mbyte/s per Bridge
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