HSI - Processing
Introduction
Commercial processors will be required at the second and third level of
triggering. The data acquisition system will probably use hardware to control
the data flow, however processors will be required for monitoring and control
of the system. Second level triggering requires very low latency for a large
number of small data transfers with good connectivity between the processors.
Level three will have a small number of large transfers and requires only
limited processor interconnectivity. Since the processors will be commercially
available chips, boards or systems, the key issues are then interfacing these
components into the trigger and data acquisition system.
The processor/interface should
- Announce it's availability to process events
- Lock buffers into physical memory
- Set up scatter/gather table
- Implement a error history memory
- Accept event fragments, DMA into memory
- 'know' when the event fragments have all arrived (or timeout)
- Interrupt the operating system
Processors for Different technologies
Click on one of the following to get more info on the specific technology:
Reiner Hauser (Reiner.Hauser@cern.ch)