-- -- Copyright (C) 1988-1998 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to -- the intellectual property, including patents, copyrights, trademarks, -- trade secrets, or maskworks, embodied in any such megafunction design, -- net list, support information, device programming or simulation file, or -- any other related documentation or information provided by Altera or a -- megafunction partner, remains with Altera, the megafunction partner, or -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. -- CHIP ldc BEGIN |g4 : OUTPUT_PIN = 186; |hp_smrst0_n : INPUT_PIN = 184; |G26 : OUTPUT_PIN = 204; |g24 : OUTPUT_PIN = 16; |HP_CAV_N : INPUT_PIN = 202; |HP_DAV_N : INPUT_PIN = 203; |HP_ERROR : INPUT_PIN = 199; |FLOWCTLED_N : OUTPUT_PIN = 133; |LUPLED_N : OUTPUT_PIN = 134; |DERRLED_N : OUTPUT_PIN = 135; |TESTLED_N : OUTPUT_PIN = 136; |LDERR_N : OUTPUT_PIN = 47; |LDOWN_N : OUTPUT_PIN = 54; |LWEN_N : OUTPUT_PIN = 55; |LCTRL_N : OUTPUT_PIN = 56; |HP_SMRST1_N : OUTPUT_PIN = 187; |AD_CONVST_N : OUTPUT_PIN = 168; |UTDO_N : INPUT_PIN = 115; |UXOFF_N : INPUT_PIN = 111; |URESET_N : INPUT_PIN = 112; |HP_LINKRDY_N : INPUT_PIN = 180; |ck40ttl : OUTPUT_PIN = 144; |g25 : OUTPUT_PIN = 10; |g23 : OUTPUT_PIN = 19; |g22 : OUTPUT_PIN = 53; |g21 : OUTPUT_PIN = 103; |g20 : OUTPUT_PIN = 104; |g19 : OUTPUT_PIN = 128; |g18 : OUTPUT_PIN = 131; |g17 : OUTPUT_PIN = 132; |g16 : OUTPUT_PIN = 141; |g15 : OUTPUT_PIN = 142; |g14 : OUTPUT_PIN = 143; |g13 : OUTPUT_PIN = 147; |g12 : OUTPUT_PIN = 148; |g11 : OUTPUT_PIN = 149; |g10 : OUTPUT_PIN = 150; |g9 : OUTPUT_PIN = 164; |g8 : OUTPUT_PIN = 166; |g7 : OUTPUT_PIN = 174; |g6 : OUTPUT_PIN = 175; |g5 : OUTPUT_PIN = 179; |g3 : OUTPUT_PIN = 197; |g2 : OUTPUT_PIN = 206; |g1 : OUTPUT_PIN = 207; |g0 : OUTPUT_PIN = 208; |udw1 : INPUT_PIN = 116; |udw0 : INPUT_PIN = 119; |qclk : INPUT_PIN = 79; |ld0 : OUTPUT_PIN = 102; |ld1 : OUTPUT_PIN = 101; |ld2 : OUTPUT_PIN = 100; |ld3 : OUTPUT_PIN = 99; |ld4 : OUTPUT_PIN = 97; |ld5 : OUTPUT_PIN = 96; |ld6 : OUTPUT_PIN = 95; |ld7 : OUTPUT_PIN = 94; |ld8 : OUTPUT_PIN = 93; |ld9 : OUTPUT_PIN = 92; |ld10 : OUTPUT_PIN = 90; |ld11 : OUTPUT_PIN = 89; |ld12 : OUTPUT_PIN = 88; |ld13 : OUTPUT_PIN = 87; |ld14 : OUTPUT_PIN = 86; |ld15 : OUTPUT_PIN = 85; |ld16 : OUTPUT_PIN = 83; |ld17 : OUTPUT_PIN = 75; |ld18 : OUTPUT_PIN = 74; |ld19 : OUTPUT_PIN = 73; |ld20 : OUTPUT_PIN = 71; |ld21 : OUTPUT_PIN = 70; |ld22 : OUTPUT_PIN = 69; |ld23 : OUTPUT_PIN = 68; |ld24 : OUTPUT_PIN = 67; |ld25 : OUTPUT_PIN = 65; |ld26 : OUTPUT_PIN = 64; |ld27 : OUTPUT_PIN = 63; |ld28 : OUTPUT_PIN = 62; |ld29 : OUTPUT_PIN = 61; |ld30 : OUTPUT_PIN = 60; |ld31 : OUTPUT_PIN = 58; |lclk : OUTPUT_PIN = 57; |hp_d0 : INPUT_PIN = 46; |hp_d1 : INPUT_PIN = 45; |hp_d2 : INPUT_PIN = 44; |hp_d3 : INPUT_PIN = 41; |hp_d4 : INPUT_PIN = 40; |hp_d5 : INPUT_PIN = 39; |hp_d6 : INPUT_PIN = 38; |hp_d7 : INPUT_PIN = 31; |hp_d8 : INPUT_PIN = 30; |hp_d9 : INPUT_PIN = 29; |hp_d10 : INPUT_PIN = 28; |hp_d11 : INPUT_PIN = 27; |hp_d12 : INPUT_PIN = 26; |hp_d13 : INPUT_PIN = 25; |hp_d14 : INPUT_PIN = 24; |hp_d15 : INPUT_PIN = 18; |hp_d16 : INPUT_PIN = 17; |hp_d17 : INPUT_PIN = 13; |hp_d18 : INPUT_PIN = 12; |hp_d19 : INPUT_PIN = 11; |url3 : INPUT_PIN = 120; |url2 : INPUT_PIN = 121; |url1 : INPUT_PIN = 122; |url0 : INPUT_PIN = 127; |tp5 : INPUT_PIN = 157; |tp4 : INPUT_PIN = 158; |tp3 : INPUT_PIN = 159; |tp2 : INPUT_PIN = 161; |tp1 : INPUT_PIN = 162; |fr_rxsys1 : INPUT_PIN = 160; |fr_rxsys0 : INPUT_PIN = 163; |fr_rxsigdet : INPUT_PIN = 167; |ad_sclk : OUTPUT_PIN = 169; |ad_rdwr : OUTPUT_PIN = 170; |ad_oti : INPUT_PIN = 172; |hp_div1 : OUTPUT_PIN = 191; |hp_div0 : OUTPUT_PIN = 190; |ad_dio : INPUT_PIN = 173; |hp_loopen : OUTPUT_PIN = 176; |hp_eqen : OUTPUT_PIN = 177; |hp_strbout : INPUT_PIN = 183; |hp_m20sel : OUTPUT_PIN = 189; |hp_tclksel : OUTPUT_PIN = 192; |hp_tclk : OUTPUT_PIN = 193; |hp_stat0 : INPUT_PIN = 195; |hp_stat1 : INPUT_PIN = 196; |hp_flagsel : OUTPUT_PIN = 198; |hp_ff : INPUT_PIN = 200; |hp_flag : INPUT_PIN = 205; DEVICE = EPF10K30AQC208-1; END; DEFAULT_DEVICES BEGIN AUTO_DEVICE = EPF10K250ABC600-1; AUTO_DEVICE = EPF10K250AGC599-1; AUTO_DEVICE = EPF10K130VBC600-2; AUTO_DEVICE = EPF10K130VGC599-2; AUTO_DEVICE = EPF10K100ABC600-1; AUTO_DEVICE = EPF10K100AFC484-1; AUTO_DEVICE = EPF10K100ABC356-1; AUTO_DEVICE = EPF10K100ARC240-1; AUTO_DEVICE = EPF10K50VBC356-1; AUTO_DEVICE = EPF10K50VRC240-1; AUTO_DEVICE = EPF10K30AFC484-1; AUTO_DEVICE = EPF10K30ABC356-1; AUTO_DEVICE = EPF10K30AFC256-1; AUTO_DEVICE = EPF10K30AQC240-1; AUTO_DEVICE = EPF10K30AQC208-1; AUTO_DEVICE = EPF10K30ATC144-1; AUTO_DEVICE = EPF10K10AFC256-1; AUTO_DEVICE = EPF10K10AQC208-1; AUTO_DEVICE = EPF10K10ATC144-1; AUTO_DEVICE = EPF10K10ATC100-1; ASK_BEFORE_ADDING_EXTRA_DEVICES = ON; END; TIMING_POINT BEGIN DEVICE_FOR_TIMING_SYNTHESIS = EPF10K30AQC208-1; |HP_STRBOUT : FREQUENCY = 80Mhz; MAINTAIN_STABLE_SYNTHESIS = OFF; CUT_ALL_CLEAR_PRESET = ON; CUT_ALL_BIDIR = ON; END; IGNORED_ASSIGNMENTS BEGIN FIT_IGNORE_TIMING = ON; DEMOTE_SPECIFIC_LCELL_ASSIGNMENTS_TO_LAB_ASSIGNMENTS = OFF; IGNORE_LOCAL_ROUTING_ASSIGNMENTS = OFF; IGNORE_DEVICE_ASSIGNMENTS = OFF; IGNORE_LC_ASSIGNMENTS = OFF; IGNORE_PIN_ASSIGNMENTS = OFF; IGNORE_CHIP_ASSIGNMENTS = OFF; IGNORE_TIMING_ASSIGNMENTS = OFF; IGNORE_LOGIC_OPTION_ASSIGNMENTS = OFF; IGNORE_CLIQUE_ASSIGNMENTS = OFF; END; LOGIC_OPTIONS BEGIN |HP_DAV_N : FAST_IO = ON; |LDOWN_N : FAST_IO = ON; |LDERR_N : FAST_IO = ON; |qclk : GLOBAL_SIGNAL = ON; |ld9 : FAST_IO = ON; |ld8 : FAST_IO = ON; |ld7 : FAST_IO = ON; |ld6 : FAST_IO = ON; |ld5 : FAST_IO = ON; |ld4 : FAST_IO = ON; |ld31 : FAST_IO = ON; |ld30 : FAST_IO = ON; |ld3 : FAST_IO = ON; |ld29 : FAST_IO = ON; |ld28 : FAST_IO = ON; |ld27 : FAST_IO = ON; |ld26 : FAST_IO = ON; |ld25 : FAST_IO = ON; |ld24 : FAST_IO = ON; |ld23 : FAST_IO = ON; |ld22 : FAST_IO = ON; |ld21 : FAST_IO = ON; |ld20 : FAST_IO = ON; |ld2 : FAST_IO = ON; |ld19 : FAST_IO = ON; |ld18 : FAST_IO = ON; |ld17 : FAST_IO = ON; |ld16 : FAST_IO = ON; |ld15 : FAST_IO = ON; |ld14 : FAST_IO = ON; |ld13 : FAST_IO = ON; |ld12 : FAST_IO = ON; |ld11 : FAST_IO = ON; |ld10 : FAST_IO = ON; |ld1 : FAST_IO = ON; |ld0 : FAST_IO = ON; |hp_div1 : FAST_IO = ON; |hp_div0 : FAST_IO = ON; |hp_d9 : FAST_IO = ON; |hp_d8 : FAST_IO = ON; |hp_d7 : FAST_IO = ON; |hp_d6 : FAST_IO = ON; |hp_d5 : FAST_IO = ON; |hp_d4 : FAST_IO = ON; |hp_d3 : FAST_IO = ON; |hp_d2 : FAST_IO = ON; |hp_d19 : FAST_IO = ON; |hp_d18 : FAST_IO = ON; |hp_d17 : FAST_IO = ON; |hp_d16 : FAST_IO = ON; |hp_d15 : FAST_IO = ON; |hp_d14 : FAST_IO = ON; |hp_d13 : FAST_IO = ON; |hp_d12 : FAST_IO = ON; |hp_d11 : FAST_IO = ON; |hp_d10 : FAST_IO = ON; |hp_d1 : FAST_IO = ON; |hp_d0 : FAST_IO = ON; |hp_strbout : GLOBAL_SIGNAL = ON; END; GLOBAL_PROJECT_DEVICE_OPTIONS BEGIN FLEX_CONFIGURATION_EPROM = AUTO; MAX7000AE_ENABLE_JTAG = ON; MAX7000AE_USER_CODE = FFFFFFFF; FLEX6000_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; FLEX10KA_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = ON; FLEX10K_USE_LOW_VOLTAGE_CONFIGURATION_EPROM = OFF; FLEX6000_ENABLE_JTAG = OFF; CONFIG_SCHEME_FLEX_6000 = PASSIVE_SERIAL; MULTIVOLT_IO = OFF; MAX7000S_ENABLE_JTAG = ON; FLEX10K_ENABLE_LOCK_OUTPUT = OFF; MAX7000S_USER_CODE = FFFF; CONFIG_SCHEME_10K = PASSIVE_SERIAL; FLEX10K_JTAG_USER_CODE = 7F; ENABLE_INIT_DONE_OUTPUT = OFF; ENABLE_CHIP_WIDE_OE = OFF; ENABLE_CHIP_WIDE_RESET = OFF; nCEO = UNRESERVED; CLKUSR = UNRESERVED; ADD17 = UNRESERVED; ADD16 = UNRESERVED; ADD15 = UNRESERVED; ADD14 = UNRESERVED; ADD13 = UNRESERVED; ADD0_TO_ADD12 = UNRESERVED; SDOUT = RESERVED_DRIVES_OUT; RDCLK = UNRESERVED; RDYnBUSY = UNRESERVED; nWS_nRS_nCS_CS = UNRESERVED; DATA1_TO_DATA7 = UNRESERVED; DATA0 = RESERVED_TRI_STATED; FLEX8000_ENABLE_JTAG = OFF; CONFIG_SCHEME = ACTIVE_SERIAL; DISABLE_TIME_OUT = OFF; ENABLE_DCLK_OUTPUT = OFF; RELEASE_CLEARS = OFF; AUTO_RESTART = OFF; USER_CLOCK = OFF; SECURITY_BIT = OFF; RESERVED_PINS_PERCENT = 0; RESERVED_LCELLS_PERCENT = 0; END; GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS BEGIN ONE_HOT_STATE_MACHINE_ENCODING = ON; STYLE = mystyle; DEVICE_FAMILY = FLEX10KA; MULTI_LEVEL_SYNTHESIS_MAX9000 = ON; AUTO_IMPLEMENT_IN_EAB = OFF; AUTO_OPEN_DRAIN_PINS = ON; AUTO_REGISTER_PACKING = OFF; AUTO_FAST_IO = OFF; AUTO_GLOBAL_OE = ON; AUTO_GLOBAL_PRESET = ON; AUTO_GLOBAL_CLEAR = ON; AUTO_GLOBAL_CLOCK = ON; MULTI_LEVEL_SYNTHESIS_MAX5000_7000 = OFF; OPTIMIZE_FOR_SPEED = 5; END; COMPILER_PROCESSING_CONFIGURATION BEGIN PRESERVE_ALL_NODE_NAME_SYNONYMS = OFF; FITTER_SETTINGS = NORMAL; SMART_RECOMPILE = OFF; GENERATE_AHDL_TDO_FILE = OFF; RPT_FILE_USER_ASSIGNMENTS = ON; RPT_FILE_LCELL_INTERCONNECT = ON; RPT_FILE_HIERARCHY = ON; RPT_FILE_EQUATIONS = ON; LINKED_SNF_EXTRACTOR = OFF; OPTIMIZE_TIMING_SNF = OFF; TIMING_SNF_EXTRACTOR = ON; FUNCTIONAL_SNF_EXTRACTOR = OFF; DESIGN_DOCTOR_RULES = EPLD; DESIGN_DOCTOR = OFF; END; COMPILER_INTERFACES_CONFIGURATION BEGIN VHDL_OUTPUT_DELAY_CONSTRUCTS = SDF_1.0; VHDL_NETLIST_WRITER = ON; NETLIST_OUTPUT_TIME_SCALE = 0.1ns; EDIF_INPUT_SHOW_LMF_MAPPING_MESSAGES = OFF; EDIF_BUS_DELIMITERS = []; EDIF_FLATTEN_BUS = OFF; EDIF_OUTPUT_FORCE_0NS_DELAYS = OFF; EDIF_OUTPUT_INCLUDE_SPECIAL_PRIM = OFF; EDIF_OUTPUT_MAP_ILLEGAL_CHAR = OFF; EDIF_OUTPUT_DELAY_CONSTRUCTS = EDO_FILE; EDIF_OUTPUT_USE_EDC = OFF; EDIF_INPUT_USE_LMF2 = OFF; EDIF_INPUT_USE_LMF1 = OFF; EDIF_OUTPUT_GND = GND; EDIF_OUTPUT_VCC = VCC; EDIF_INPUT_GND = GND; EDIF_INPUT_VCC = VCC; EDIF_OUTPUT_EDC_FILE = *.edc; EDIF_INPUT_LMF2 = *.lmf; EDIF_INPUT_LMF1 = *.lmf; VHDL_GENERATE_CONFIGURATION_DECLARATION = OFF; VERILOG_OUTPUT_DELAY_CONSTRUCTS = VO_FILE; VHDL_FLATTEN_BUS = OFF; VERILOG_FLATTEN_BUS = OFF; EDIF_TRUNCATE_HIERARCHY_PATH = OFF; VHDL_TRUNCATE_HIERARCHY_PATH = OFF; VERILOG_TRUNCATE_HIERARCHY_PATH = OFF; VERILOG_OUTPUT_MAP_ILLEGAL_CHAR = OFF; VHDL_WRITER_VERSION = VHDL87; VHDL_READER_VERSION = VHDL87; SYNOPSYS_MAPPING_EFFORT = MEDIUM; SYNOPSYS_BOUNDARY_OPTIMIZATION = OFF; SYNOPSYS_HIERARCHICAL_COMPILATION = ON; SYNOPSYS_DESIGNWARE = OFF; SYNOPSYS_COMPILER = DESIGN; USE_SYNOPSYS_SYNTHESIS = OFF; VERILOG_NETLIST_WRITER = OFF; XNF_GENERATE_AHDL_TDX_FILE = ON; XNF_TRANSLATE_INTERNAL_NODE_NAMES = ON; XNF_EMULATE_TRI_STATE_BUSES = INTERNAL_LOGIC; EDIF_OUTPUT_VERSION = 200; EDIF_NETLIST_WRITER = OFF; END; CUSTOM_DESIGN_DOCTOR_RULES BEGIN MASTER_RESET = OFF; EXPANDER_NETWORKS = ON; RACE_CONDITIONS = ON; DELAY_CHAINS = ON; ASYNCHRONOUS_INPUTS = ON; PRESET_CLEAR_NETWORKS = ON; STATIC_HAZARDS_AFTER_SYNTHESIS = OFF; STATIC_HAZARDS_BEFORE_SYNTHESIS = ON; MULTI_CLOCK_NETWORKS = ON; MULTI_LEVEL_CLOCKS = ON; GATED_CLOCKS = ON; RIPPLE_CLOCKS = ON; END; SIMULATOR_CONFIGURATION BEGIN END_TIME = 5.0us; START_TIME = 0.0ns; GLITCH_TIME = 0.0ns; GLITCH = OFF; OSCILLATION_TIME = 0.0ns; OSCILLATION = OFF; CHECK_OUTPUTS = OFF; SETUP_HOLD = OFF; USE_DEVICE = OFF; END; TIMING_ANALYZER_CONFIGURATION BEGIN ANALYSIS_MODE = REGISTERED_PERFORMANCE; CUT_OFF_RAM_REGISTERED_WE_PATHS = OFF; LIST_PATH_FREQUENCY = 10MHz; LIST_PATH_COUNT = 10; REGISTERED_PERFORMANCE_OPTIONS = NUMBER_OF_PATHS; INCLUDE_PATHS_LESS_THAN_VALUE = 214.7483647ms; INCLUDE_PATHS_LESS_THAN = OFF; INCLUDE_PATHS_GREATER_THAN_VALUE = 0.0ns; INCLUDE_PATHS_GREATER_THAN = OFF; DELAY_MATRIX_OPTIONS = SHOW_ALL_PATHS; CELL_WIDTH = 18; LIST_ONLY_LONGEST_PATH = ON; CUT_OFF_CLEAR_AND_PRESET_PATHS = ON; CUT_OFF_IO_PIN_FEEDBACK = ON; AUTO_RECALCULATE = OFF; END; OTHER_CONFIGURATION BEGIN EXPLICIT_FAMILY = 1; LAST_MAXPLUS2_VERSION = 9.0; FLEX_10K_52_COLUMNS = 40; DEFAULT_9K_EXP_PER_LCELL = 1/2; LOCAL_INTERCONNECT_PER_LAB_PERCENT = 100; LCELLS_PER_ROW_PERCENT = 100; FAN_IN_PER_LCELL_PERCENT = 100; EXP_PER_LCELL_PERCENT = 100; ROW_PINS_PERCENT = 50; ORIGINAL_MAXPLUS2_VERSION = 9.0; COMPILER_DATA = "1,1,0,1,0,0,0,1,1,1,1,0,1,1,1"; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX5000 BEGIN REGISTER_OPTIMIZATION = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; RESYNTHESIZE_NETWORK = ON; MULTI_LEVEL_FACTORING = ON; SUBFACTOR_EXTRACTION = ON; REFACTORIZATION = ON; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = ON; REDUCE_LOGIC = ON; DECOMPOSE_GATES = ON; SOFT_BUFFER_INSERTION = ON; FAST_IO = OFF; IGNORE_SOFT_BUFFERS = OFF; PARALLEL_EXPANDERS = OFF; TURBO_BIT = OFF; XOR_SYNTHESIS = ON; SLOW_SLEW_RATE = OFF; MINIMIZATION = FULL; CARRY_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CASCADE_CHAIN = IGNORE; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.MAX7000 BEGIN REGISTER_OPTIMIZATION = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; RESYNTHESIZE_NETWORK = ON; MULTI_LEVEL_FACTORING = ON; SUBFACTOR_EXTRACTION = ON; REFACTORIZATION = ON; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = ON; REDUCE_LOGIC = ON; DECOMPOSE_GATES = ON; SOFT_BUFFER_INSERTION = ON; FAST_IO = OFF; IGNORE_SOFT_BUFFERS = OFF; PARALLEL_EXPANDERS = OFF; TURBO_BIT = ON; XOR_SYNTHESIS = ON; SLOW_SLEW_RATE = OFF; MINIMIZATION = FULL; CARRY_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CASCADE_CHAIN = IGNORE; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.CLASSIC BEGIN REGISTER_OPTIMIZATION = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; RESYNTHESIZE_NETWORK = ON; MULTI_LEVEL_FACTORING = OFF; SUBFACTOR_EXTRACTION = OFF; REFACTORIZATION = OFF; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; REDUCE_LOGIC = OFF; DECOMPOSE_GATES = ON; SOFT_BUFFER_INSERTION = ON; FAST_IO = OFF; IGNORE_SOFT_BUFFERS = OFF; PARALLEL_EXPANDERS = OFF; TURBO_BIT = ON; XOR_SYNTHESIS = OFF; SLOW_SLEW_RATE = OFF; MINIMIZATION = FULL; CARRY_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CASCADE_CHAIN = IGNORE; END; DEFINE_LOGIC_SYNTHESIS_STYLE NORMAL.FLEX8000 BEGIN REGISTER_OPTIMIZATION = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; RESYNTHESIZE_NETWORK = ON; MULTI_LEVEL_FACTORING = ON; SUBFACTOR_EXTRACTION = ON; REFACTORIZATION = ON; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = ON; REDUCE_LOGIC = ON; DECOMPOSE_GATES = ON; SOFT_BUFFER_INSERTION = ON; IGNORE_SOFT_BUFFERS = ON; PARALLEL_EXPANDERS = OFF; TURBO_BIT = OFF; XOR_SYNTHESIS = OFF; SLOW_SLEW_RATE = OFF; MINIMIZATION = FULL; CARRY_CHAIN_LENGTH = 32; CARRY_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = 2; CASCADE_CHAIN = IGNORE; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX5000 BEGIN REGISTER_OPTIMIZATION = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; RESYNTHESIZE_NETWORK = ON; MULTI_LEVEL_FACTORING = ON; SUBFACTOR_EXTRACTION = OFF; REFACTORIZATION = OFF; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = ON; REDUCE_LOGIC = ON; DECOMPOSE_GATES = ON; SOFT_BUFFER_INSERTION = ON; FAST_IO = OFF; IGNORE_SOFT_BUFFERS = OFF; PARALLEL_EXPANDERS = OFF; TURBO_BIT = OFF; XOR_SYNTHESIS = ON; SLOW_SLEW_RATE = OFF; MINIMIZATION = FULL; CARRY_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CASCADE_CHAIN = IGNORE; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.MAX7000 BEGIN REGISTER_OPTIMIZATION = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; RESYNTHESIZE_NETWORK = ON; MULTI_LEVEL_FACTORING = ON; SUBFACTOR_EXTRACTION = OFF; REFACTORIZATION = OFF; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = ON; REDUCE_LOGIC = ON; DECOMPOSE_GATES = ON; SOFT_BUFFER_INSERTION = ON; FAST_IO = OFF; IGNORE_SOFT_BUFFERS = OFF; PARALLEL_EXPANDERS = ON; TURBO_BIT = ON; XOR_SYNTHESIS = ON; SLOW_SLEW_RATE = OFF; MINIMIZATION = FULL; CARRY_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CASCADE_CHAIN = IGNORE; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.CLASSIC BEGIN REGISTER_OPTIMIZATION = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; RESYNTHESIZE_NETWORK = ON; MULTI_LEVEL_FACTORING = OFF; SUBFACTOR_EXTRACTION = OFF; REFACTORIZATION = OFF; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; REDUCE_LOGIC = OFF; DECOMPOSE_GATES = ON; SOFT_BUFFER_INSERTION = ON; FAST_IO = OFF; IGNORE_SOFT_BUFFERS = OFF; PARALLEL_EXPANDERS = OFF; TURBO_BIT = ON; XOR_SYNTHESIS = OFF; SLOW_SLEW_RATE = OFF; MINIMIZATION = FULL; CARRY_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CASCADE_CHAIN = IGNORE; END; DEFINE_LOGIC_SYNTHESIS_STYLE FAST.FLEX8000 BEGIN REGISTER_OPTIMIZATION = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; RESYNTHESIZE_NETWORK = ON; MULTI_LEVEL_FACTORING = ON; SUBFACTOR_EXTRACTION = OFF; REFACTORIZATION = OFF; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = ON; REDUCE_LOGIC = ON; DECOMPOSE_GATES = ON; SOFT_BUFFER_INSERTION = ON; IGNORE_SOFT_BUFFERS = ON; PARALLEL_EXPANDERS = OFF; TURBO_BIT = OFF; XOR_SYNTHESIS = OFF; SLOW_SLEW_RATE = OFF; MINIMIZATION = FULL; CARRY_CHAIN_LENGTH = 32; CARRY_CHAIN = AUTO; CASCADE_CHAIN_LENGTH = 2; CASCADE_CHAIN = AUTO; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX5000 BEGIN REGISTER_OPTIMIZATION = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; RESYNTHESIZE_NETWORK = OFF; MULTI_LEVEL_FACTORING = OFF; SUBFACTOR_EXTRACTION = OFF; REFACTORIZATION = OFF; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; REDUCE_LOGIC = OFF; DECOMPOSE_GATES = OFF; SOFT_BUFFER_INSERTION = OFF; FAST_IO = OFF; IGNORE_SOFT_BUFFERS = OFF; PARALLEL_EXPANDERS = OFF; TURBO_BIT = OFF; XOR_SYNTHESIS = OFF; SLOW_SLEW_RATE = OFF; MINIMIZATION = PARTIAL; CARRY_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CASCADE_CHAIN = IGNORE; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.MAX7000 BEGIN REGISTER_OPTIMIZATION = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; RESYNTHESIZE_NETWORK = OFF; MULTI_LEVEL_FACTORING = OFF; SUBFACTOR_EXTRACTION = OFF; REFACTORIZATION = OFF; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; REDUCE_LOGIC = OFF; DECOMPOSE_GATES = OFF; SOFT_BUFFER_INSERTION = OFF; FAST_IO = OFF; IGNORE_SOFT_BUFFERS = OFF; PARALLEL_EXPANDERS = OFF; TURBO_BIT = ON; XOR_SYNTHESIS = OFF; SLOW_SLEW_RATE = OFF; MINIMIZATION = PARTIAL; CARRY_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CASCADE_CHAIN = IGNORE; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.CLASSIC BEGIN REGISTER_OPTIMIZATION = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; RESYNTHESIZE_NETWORK = ON; MULTI_LEVEL_FACTORING = OFF; SUBFACTOR_EXTRACTION = OFF; REFACTORIZATION = OFF; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; REDUCE_LOGIC = OFF; DECOMPOSE_GATES = ON; SOFT_BUFFER_INSERTION = OFF; FAST_IO = OFF; IGNORE_SOFT_BUFFERS = OFF; PARALLEL_EXPANDERS = OFF; TURBO_BIT = ON; XOR_SYNTHESIS = OFF; SLOW_SLEW_RATE = OFF; MINIMIZATION = PARTIAL; CARRY_CHAIN_LENGTH = -1; CARRY_CHAIN = IGNORE; CASCADE_CHAIN_LENGTH = -1; CASCADE_CHAIN = IGNORE; END; DEFINE_LOGIC_SYNTHESIS_STYLE WYSIWYG.FLEX8000 BEGIN REGISTER_OPTIMIZATION = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; RESYNTHESIZE_NETWORK = OFF; MULTI_LEVEL_FACTORING = OFF; SUBFACTOR_EXTRACTION = OFF; REFACTORIZATION = OFF; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; REDUCE_LOGIC = OFF; DECOMPOSE_GATES = OFF; SOFT_BUFFER_INSERTION = ON; IGNORE_SOFT_BUFFERS = ON; PARALLEL_EXPANDERS = OFF; TURBO_BIT = OFF; XOR_SYNTHESIS = OFF; SLOW_SLEW_RATE = OFF; MINIMIZATION = PARTIAL; CARRY_CHAIN_LENGTH = 32; CARRY_CHAIN = MANUAL; CASCADE_CHAIN_LENGTH = 2; CASCADE_CHAIN = MANUAL; END; DEFINE_LOGIC_SYNTHESIS_STYLE mystyle.MAX5000 BEGIN REGISTER_OPTIMIZATION = ON; RESYNTHESIZE_NETWORK = ON; MULTI_LEVEL_FACTORING = ON; SUBFACTOR_EXTRACTION = ON; REFACTORIZATION = ON; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = ON; REDUCE_LOGIC = ON; DECOMPOSE_GATES = ON; SOFT_BUFFER_INSERTION = ON; CARRY_CHAIN = IGNORE; CASCADE_CHAIN = IGNORE; MINIMIZATION = FULL; FAST_IO = OFF; IGNORE_SOFT_BUFFERS = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; PARALLEL_EXPANDERS = OFF; TURBO_BIT = OFF; XOR_SYNTHESIS = ON; SLOW_SLEW_RATE = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE mystyle.MAX7000 BEGIN REGISTER_OPTIMIZATION = ON; RESYNTHESIZE_NETWORK = ON; MULTI_LEVEL_FACTORING = ON; SUBFACTOR_EXTRACTION = ON; REFACTORIZATION = ON; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = ON; REDUCE_LOGIC = ON; DECOMPOSE_GATES = ON; SOFT_BUFFER_INSERTION = ON; CARRY_CHAIN = IGNORE; CASCADE_CHAIN = IGNORE; MINIMIZATION = FULL; FAST_IO = OFF; IGNORE_SOFT_BUFFERS = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; PARALLEL_EXPANDERS = OFF; TURBO_BIT = ON; XOR_SYNTHESIS = ON; SLOW_SLEW_RATE = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE mystyle.CLASSIC BEGIN REGISTER_OPTIMIZATION = OFF; RESYNTHESIZE_NETWORK = ON; MULTI_LEVEL_FACTORING = OFF; SUBFACTOR_EXTRACTION = OFF; REFACTORIZATION = OFF; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = OFF; REDUCE_LOGIC = OFF; DECOMPOSE_GATES = ON; SOFT_BUFFER_INSERTION = ON; CARRY_CHAIN = IGNORE; CASCADE_CHAIN = IGNORE; MINIMIZATION = FULL; FAST_IO = OFF; IGNORE_SOFT_BUFFERS = OFF; USE_LPM_FOR_AHDL_OPERATORS = OFF; PARALLEL_EXPANDERS = OFF; TURBO_BIT = ON; XOR_SYNTHESIS = OFF; SLOW_SLEW_RATE = OFF; END; DEFINE_LOGIC_SYNTHESIS_STYLE mystyle.FLEX8000 BEGIN CARRY_CHAIN_LENGTH = 32; CASCADE_CHAIN_LENGTH = 2; REGISTER_OPTIMIZATION = ON; RESYNTHESIZE_NETWORK = ON; MULTI_LEVEL_FACTORING = ON; SUBFACTOR_EXTRACTION = ON; REFACTORIZATION = ON; NOT_GATE_PUSH_BACK = ON; DUPLICATE_LOGIC_EXTRACTION = ON; REDUCE_LOGIC = ON; DECOMPOSE_GATES = ON; SOFT_BUFFER_INSERTION = ON; CARRY_CHAIN = AUTO; CASCADE_CHAIN = AUTO; MINIMIZATION = FULL; IGNORE_SOFT_BUFFERS = ON; USE_LPM_FOR_AHDL_OPERATORS = OFF; PARALLEL_EXPANDERS = OFF; TURBO_BIT = OFF; XOR_SYNTHESIS = OFF; SLOW_SLEW_RATE = OFF; END;