A set of files are prepared off line containing: the packet descriptors, the configuration information for every traffic node and the routing tables for the packet switches. Prior to loading this data, the control networks for the traffic nodes and packet switches are used to verify that the expected devices are present and connected in the required order.
Each control processor has 4 Kbytes of on-chip memory. It is loaded at initialisation time with a kernel which handles the control link traffic and the dynamic loading of the application programs. Application programs for self-test, hardware configuration, storing of traffic descriptors and run time supervision are loaded in turn by the host which also controls their synchronisation.
Once the system is running each control processor maintains local histograms of results. These are returned to the host on request for on-line display, data logging and subsequent analysis.