Testbed Architecture
The Macrame network testbed consists of :
- A packet switching network based on STC104 routers
- Traffic nodes generating programmable traffic patterns
- drives one DS-Link via an STC101 parallel link adaptor chip
- traffic pattern are pre-programmed into an onboard RAM
- an FPGA reads the traffic descriptors from the RAM and feeds the link interface
- Timing nodes are used to measure latency
16 traffic nodes and an STC104 are integrated on one board
- 16 DS-Links are connected directly to the nodes
- 16 differential DS-Links are brought out to the front panel
System is implemented in VME mechanics