next up previous
Next: Low-latency context switches Up: Performance improvements Previous: Modelling the CPU load

Using the DSNIC board for packet handling

By off-loading all the packet handling to the DSNIC board, as discussed in Section 8.2, all the packet handling interrupts, which are O(nr of packets), can be avoided. Avoiding these interrupts has no effect on the communication latency, since this latency is caused by the O(nr of messages) operations. Since latency and throughput are directly coupled in Comms1, there is no effect on the throughput graph. The gain is to be expected in CPU load. For ATLAS, which requires packet size 1 Kbyte, this can result in a performance gain of up to 53 %, see Table 3. This potential gain is modelled using , see graph B in Figure 12.



Marcel Boosten
Wed Mar 11 14:25:07 MET 1998