Simplex G-LINK LDC

Protocol PLD hardware specification

 

1. Introduction

The G-LINK to S-LINK signal mapping is implemented in a ALTERA flex10K device. The first version of this logic will be as simple as possible, optimized for testing purposes. Normal data transfer will without flow control will be implemented, at full speed, both in 20 or in 16 bit modes. The lower 20 or 16 bits on the S-LINK connector are used for data reception, on the higher four bits G-LINK flags are monitored.

2. HDMP1024 G-LINK receiver configuration

2.1 Link Synchronisation

The G-LINK receiver chip will be configured to "Simplex method 3 with external reference oscillator" according to [1].

2.2 Data width

As a default the G-LINK receiver chip is set to 16-bit data reception mode, 20-bit mode can be selected by a jumper.

2.3 Flag select

As a default the Flag Bit mode is disabled on the G-LINK receiver.. Flag-bit mode can be selected by a jumper.

 

3. S-LINK Connector Signals

3.1 Data Bits (LD[31..0])

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

CAV

DAV

ERR

FLG

RL3

RL2

RL1

RL0

Res

Res

Res

Res

D19

D18

D17

D16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Abbreviations:

D[19..0] Received data word. In 16 bit mode data outputs D[19..16] are undefined

CAV Control Frame Available, active low, indicates that D[19..0] is a control word

DAV Data Available. This signal has tho behave the same way as the UWEN# signal.

ERR Received Data Error: Asserted when a word on D[19..0] does not correspond to either valid Data, Control of Fill frame encoding. When Flag Bit mode is disabled, error in flag bit alternation is also indicated on this bit.

FLG Flag Bit: In Flag Bit Mode this bit indicates the value of the transmitted flag bit and can be treated as an extra data bit. When Flag Bit Mode is disabled, this bit differentiates even frames from odd ones.

RL[3..0] The value on the URL[3..0] lines of the S-LINK connector will be sampled and transmitted to LD[27..24] outputs for test purpose.

Res Reserved bit, value is undefined

3.1 Other bits

LDERR# Asserted when a word on D[19..0] does not correspond to either valid Data, Control of Fill frame encoding. When Flag Bit mode is disabled error in flag bit alternation is also indicated on this bit. Active low.

LDOWN# Asserted if the G-LINK RX state machine start-up sequence is not complete. Active low.

LWEN# Indicates that LD[31..0] outputs have received a data word. Data should be latched on the rising edge of LCLK when LWEN# is active. Active low.

LCTRL# Not available on this version, has a constant vcc value.

LCLK Received data should be latched on the rising edge of LCLK when LWEN# is active. Connected to the STRBOUT signal of G-Link receiver

UXOFF This input is tri-stated, not available on this version

URESET This signal resets the S-LINK logic and the RX state machine in the G-LINK receiver.

UTD0# This input is tri-stated, not available on this version

UDW[1..0] These inputs are tri-stated, not available on this version. 16/20 bit mode of the G-LINK receiver can be set by a jumper. In 16 bit mode data outputs LD[19..16] are undefined.

URL[3..0] No return lines are implemented on this version. The value on these lines vill be sampled and transmitted to LD[27..24] outputs for test purpose.

 

References

[1] Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os Technical Data
Hewlett Packard HDMP-1022 Transmitter and HDMP-1024 Receiver Data Sheet