Simplex G-Link S-LINK Link Destination Card Data Sheet


This Data Sheet describes a Simplex S-Link LDC which is using the HP G-Link HDMP-1024 receiver and optical or electrical physical media.

Data Transfer Rate

The maximum clock rate (LCLK) is 40 Mhz. Minimum frequency of LCLK is  29.2 Mhz.
Since it is a simplex link, flow control is not available. The UXOFF# input is ignored. LFF# on the LSC indicates that the input FIFO is full. LFF# will always be inactive (logic high) in 16 bit mode.

Data Width Options

This S-Link is of switchable width and can be operated in the following two modes: The user has to make sure that the data width (UDW[1..0] inputs) have the same setting on both LSC and LDC.

Operation Modes

Link synchronisation mode can be selected with a jumper.
TP3 is removed (default): Link Synchronisation with synchronous pulses (Fill Frames). The LSC must send Fill Frames for ~1ms to synchronise LDC.
TP3 is inserted: Link Synchronisation with on-board reference oscillator. UCLK must be 40 Mhz. LSC does not need to send fill frames. The link will work without using URESET# signal on the LSC.

Mapping into G-Link

This information is necessary for the Link Source Card implementation.
20 bit single frame G-Link mode is used, odd parity of each four bits of LD[15..0] are sent on the LD[19..16] lines respectively for error detection (E.g. LD16 is the odd parity of LD[3...0]).
When 32bit S-LINK data width is selected (by the UDW[1..0] lines), 32 bit S-Link words are sent in two 20 bit G-Link word. The G-Link FLAG indicates which half of the S-Link word has been received. The logic high value of FLAG means that the received word is sent from UD[31..16] of the S-LINK LSC so the LDC will write it to LD[31..16]. In this mode the LSC will pull the Link Full Flag (LFF#) down whenever its input FIFO is full, which may mean that that LFF# goes low on every other dataword.  S-LINK control words are mapped into G-Link control words. Bits 19-18 are reserved for G-Link, bit 17 differentiate a test control word (0) from a normal control word (1) and bit 16 is the odd parity of bits 15-0. The user receives only the data part of the control word on LD[15..4] according to the S-Link specification..
D[19..18] D[17] D16 D[15..4] D[3..0]
Reserved for G-Link 0 => Test Control Word  Odd parity of LD[15..0] Rx Data Reserved for S-LINK
 Table 3: Control word transmission

Selftest Mode

Selftest mode is implemented in all operation modes according to the S-LINK specification. Test Data is Checked and the Data Error Led is illuminated and the LDERR# signal is pulled down on test data comparison error.

Return Lines

As this is a simplex S-Link, the Return Lines are not used.

Error Detection

Word by word error reporting is implemented using the "Error" signal of G-Link and parity checking. Four parity bits are transmitted with the datawords, parity is checked in each half byte (4 bits) on the transmitted word. One parity bit is transmitted with each control word.

Led Indicators

 Last Updated on 30.06.1999 by Zoltán Meggyesi