1.    Introduction

The HOLA S-LINK interface is a standard S-LINK implementation which uses the TI TLK2501 2.5 Gbps transceiver both for the forward and for the return channel (one per card). For the optical transmission Small Form Factor Pluggable (SFP) Multimode transceivers with LC Connector are used. HOLA S-LINK can transfer with one duplex fibre at the full S-LINK bandwidth of 160MB/s.

More information, including this document, about the HOLA Interface can be found on the World Wide Web at:

The reader of this document should know the basics of the S-LINK specification. This data sheet only points out a few important features of HOLA and makes a few clarifications. The S-Link specification can be downloaded from the Worldwide Web at:

2.    Main Features

The S-LINK code for the HOLA cards is:

The main features of the HOLA S-LINK implementation are:
 

            General features

• Duplex S-Link
• 32-bit data width
• UCLK up to 40 MHz
• LCLK 40 MHz
• 160 MByte/s maximum data rate
• 125 MByte/s transmission rate for control information (UCTRL# low)
• 15.5 MHz sampling rate for the return lines
• 3.3V supply voltage
• Block basis error reporting on data words
• Word-by-word error reporting on control words
• Autonomous link synchronization and maintenance of physical link
• Test function for the return lines
• Autonomous link synchronization and maintenance of physical link
• Improved S-LINK Reset protocol
• Flow control is provided both in data mode and self test modes
• Only one duplex fibre needed for full S-LINK bandwidth of 160 MB/s
• Optical output, max. cable length with 50µm multimode cables: 300m

3.    Installation

Fix the HOLA S-LINK cards with screws to standoff pillars and front panel mounting holes to avoid mechanical stress and contact problems. For proper operation the board should be fixed by all four screws. Avoid mechanical stress on the cards during mounting. Do not plug in and out the cards on the motherboard when this is powered on.

Connect the optical fiber or electrical cable and after powering up the cards the link goes up immediately and Power and Link up leds go on. There is no need for a reset at power up as the cards go up when powered on and fibers are connected.
 

4.    Operating Conditions
 

 5.    Timing characteristics

Table 5-1 gives the required timing parameter for LSC for proper operation. See [1] for explanation of the parameters.
 

 Table 5-2 gives the guaranteed timing parameters for LDC.
 

  6.    Optical characteristics
 
 

(*) Maximum optical length is 400 m, limited to 300 m by the FIFO in LDC (see chapter 12)
 

 7.    LED Indicators

Apart from the S-Link specified LEDs, HOLA cards contain an extra LED (ACT - Activity LED). This LED will be illuminated when a write operation was performed on the FIFO in the previous 2¹⁴ clock cycles. For the LSC, that means aprox. 410 us, for a 40 MHz UCLK clock. For the LSC, that means 131 us.

Furthermore, ERR  LED on the LSC is active (unused in the S-LINK specification), and will indicate that the FIFO is completely full, because the user has tried to write more than the 32 words allowed after LFF# set.
 

 8.    User Data Width Lines

The UDW input lines are unused. If HOLA is set to 16 or 8-bit mode the effective transmission rate will go down accordingly since all 32 bits always are transferred.
 

9.    Data Transfer

The HOLA S-LINK will transfer all input data when up, Power and Link Up LEDs are on and LDOWN# lines are high on both sides. If data is written to anLSC faster than 40 MHz the LFF# flag may go low and the XOFF led goes on at the LSC, even if there is no flow control sent from LDC. This is because maximum data transmission rate is 160 Mbytes/s.

The by the S-LINK specified two words after LFF# being asserted are modified. Up to 32 more words can be written to an HOLA LSC after LFF# goes low.

For small data block sizes the LFF# line will also become active as error detection and S-LINK control words take up bandwidth.
 

10.    S-LINK Reset

The HOLA S-LINK features an improved reset protocol, which is compatible to the protocol as described in [1]. The user may reset the whole link from either side, or even both sides. The card reset is changed into a link reset to make the reset an easy and reliable operation.

If the link is down prior to the reset cycle, LDC will come up before LSC, regardless of which side the reset is performed. This eliminates the chance of data written to LSC being lost when the LDC is still down.

If the link is up prior to the reset cycle, the card where URESET# line is asserted will go down according to [1]. The other side will be reset without going down.

It is not recommended to perform a reset while writing data to the LSC, as this will cause data loss.
 

11.    Test Mode

Self-test mode in the forward channel fully complies with S-LINK specification. Furthermore, test mode is also performed on the return channel. An error in the return channel will force the LSC to send continuosly wrong test words, causing an error on the LDC.
 

12.    Flow Control

The LDC includes a 512-word FIFO. A flow control request will be sent when more than 256 words are stored, and not directly when XOFF# coming from the Read-Out motherboard (ROMB) is set. Therefore, the ROMB does not need to compensate the reaction time of the whole link, but only the response time of the LDC. This margin introduces a constraint for the maximum cable length. For a buffer of 256 words the maximum length, as calculated below, is 300 m.

The maximum cable length can be calculated from the formula given in [1]:
 
 

Where:

RBS = FIFO margin (words)
LDC_rt = LDC reaction time to send XOFF after FIFO sets full flag (ns).
LSC_rt = LSC reaction time to stop transmitting data after XOFF received (ns).
L = Length of S-LINK (m).
UFD = Unit Fibre Delay - time for light to travel 1m in fibre (approx. 6 ns/m).
DTR = Data Transfer Rate (ns/word).

Data words in LSC and LDC pipelines are included in LSC_rt and LDC_rt respectively.
 
 

13.    Return Lines

Return Lines are always functional, even when link is down and during test mode. An internal parity checking logic ensures proper operation of the Return Lines. The sampling rate of the return lines is 15.5 MHz in normal mode and 7 MHz during test mode.
 

14.    Error Detection

HOLA features a CRC-based block error detection and errors are reported in the following control word, as specified in [1].

S-LINK control words uses parity bits as error detection in order to separate data errors from control word errors.
 

15.    Link Down Function

The following events may result the link down signal to be asserted:

1. Reset cycle
2. Self-test mode
3. Local reset, i.e. the LDOWN# is asserted only on the card where URESET# is set low.
4. LSC or LDC is not powered up
5. Broken optical link
6. Fatal error occurred
 

16.    Known Bugs

For the moment there are no known bugs.

References

[1]. O. Boyle, R. McLaren, E. van der Bij, "The S-LINK Interface Specification",
http://www.cern.ch/HSI/s-link/spec/spec/ CERN, 1997.