Source files

The source files are written in Verilog HDL. Galileo3.24 is used to generate the .tdf files, which are required by MaxplusII to generate the final bit stream that goes into the configuration PROM of the Altera.

The following is a detailed description of the steps that go from generating or editing a file in the Verilog HDL format until the generation of the bitstream with Altera's Max+Plus II.

1. Make the required changes on the file (ending with .v) concerned.

2. Start Galileo3.24 and click on 'Logic Explorer'; a window called Galileo Logic Explorer will appear.

3. Under the section 'INPUT DESIGN' select first 'Verilog' in the pull-down menu in the field 'Format:'. Now select the name of the file that has changed with the pull-down menu in the field 'File Name:'. Leave the field 'Technology:' blank.

4. Under the section 'OUTPUT DESIGN' select 'Altera FLEX 10K' under the field 'Technology:' and 'AHDL' under the field 'Format:'. The name of the file in the field 'File Name:' should be the same as in the 'INPUT DESIGN' section, but with the extension '.tdf' instead.

5. Under the section 'CONTROL FILE' leave the field 'File Name:' blank.

6. Under the section 'RUNTIME OPTIONS' select 'Delay' and 'Standard'.

7. Click on 'Synthesis opts...'. A window will appear. Make sure that 'Mode:' is set to 'Macro' EXCEPT for the case where the file to be processed is altera.v. Should this be the case then the mode must be set to 'Chip'. Click on 'Apply'.

8. Click on 'Input opts...'. A window will appear. Check the boxes 'Full Case' and 'Parallel Case' in the section 'Synthesis Switches:'. Click on 'Apply'.

9. Now click on 'Run...' in the window 'Galileo Logic Explorer'. This will generate the file .tdf out of the file .v.

10. If the change in the file involved a change in the interface of the module (name or ordering of signals), make the corresponding changes on the files where this module is instantiated. Every file that is edited must be recompiled as it has been explained here.