Transition module with no link cards mounted.
(with two LDCs and one LDC)
|The S-LINK to VME64x board (S2VME64x) is a VME64x transition
module that has slots for four S-LINK link cards. Each slot can either
be fitted with a Link Source Card or and Link Destination Card. The transition
module fits on the backside of the new
Extensions crates. It will be used whenever I/O has to be connected
to the back of a crate. Notably the ATLAS Read-out Driver and Read-out
Buffer devices can make use of this transition module.
The VME64 Extensions crate uses 5-row connectors for P1 and P2, while
P3 is freely definable. For this application, also for P3 a 5-row connector
The S-LINK pin mapping has been designed for having low cross-talk and high signal quality. E.g. the clock lines are surrounded by ground pins and the signal lines need a minimal amount of crossings between the S-LINK and P2/P3 connectors. The S2VME64x is completely passive. It has series resistors in the signal lines to improve the signal quality. The S2VME64x is powered via the P2 connector and P3 connectors.
Originally there was also a plan to develop a 3U transition module that can carry only one S-LINK, but as there is no direct demand for it, this board will not be designed.
The transtion module features:
|22 September 1999||S-LINK signal mapping to 5-row P2/P3 defined|
|24 January 2000||Order of the backplane with 5-row connectors will be delayed until more support from the detectors for such a solution will come. Now looking at a transition module using a 5-row P2 and a 3-row P3 (using a cheaper standard P2 backplane), which will be able to handle only three S-LINKs in total.|
|17 February 2000||New mapping defined that can handle one S-LINK on a 3-row connector and two S-LINKs on a 5-row connector. The 3-row pinout is compatible with the 5-row layout. Also there a five user-defineable signals available on rows A and C.|
|11 April 2000||Will design first a transition module using the original 5-row connector only layout as this will be used by the ATLAS LArg ROD. Schematics being drawn. Pre-layout signal quality simulations finished.|
|3 May 2000||Schematics reviewed by Erik van der Bij. Submitted design for PCB layout|
|21 June 2000||PCB design finished. PCB design reviewed by Silvio Orsi, Patrick
Donnat and Erik van der Bij.
Submitted for production of 5 PCBs
|28 June 2000||PCB submission was delayed for one week because of library problems|
|8 August 2000||Received PCB and front-panel. Mechanics OK. Given for assembly|
|18 August 2000||Three boards mounted. Will be given to LArg ROD for test.
A new project is started (Sept 2000) to make a similar module which has four input slots that move data in an Altera that can reformat the data and send it over the two P2 S-LINK channels. This module will also have an ODIN LSC integrated on the board, which gets its data from P3. This module may be used by the ATLAS Tilecal.
|22 September 2000||One module given to University of Geneva LArg ROD. Preliminary tests show board is working.|
|2 February 2001||The LArg ROD has sucessfully sent data to a test program on a RIO using the S2VME64x and the custom-made 4-slot VME64-Extensions backplane|
|17 January 2000||The S2VME64x is a stand-alone hardware device. No software is needed|
CERN - High Speed Interconnect
Erik van der Bij - 7 March 2001