4.0 S-LINK Usage Instructions

4.11 Reset Function

An asynchronous reset is provided on the LSC and LDC on the line URESET#. At the LSC, when URESET# is set low, the LSC sets LDOWN# low to prevent data being transferred to the LSC. This happens within four clock cycles of UCLK. The LSC then initialises. When initialisation is complete, the LSC sets LDOWN# high. This is a signal to the FEMB that it can now remove the reset by setting URESET# high. After URESET# has been set high, the FEMB shall wait at least four clock cycles of UCLK before setting UWEN# low to transfer data to the LSC.

At the LDC, a similar procedure is followed: The ROMB sets URESET# low and the LDC responds by setting LDOWN# low and then initialising. When initialisation is complete, the LDC sets LDOWN# high.

If URESET# is set low on either S-LINK card, this should cause LDOWN# to be set low on the other S-LINK card. The other card will then have to be reset to clear LDOWN#.

This procedure is shown in Figure 7 and the values of the timing parameters are given in Table 12.

For a duplex S-LINK, the LSC and LDC can be reset in any order. For a simplex S-LINK, the LDC shall be reset first.

FIGURE 7. Reset procedure at the LSC and LDC

TABLE 12. Reset Cycle Timing Parameters
Symbol Description Min Max Units
tRL URESET# low to LDOWN# low 4 Cycles of UCLK or LCLK
tRU URESET# high to UWEN# low 4 Cycles of UCLK or LCLK
tINIT URESET# low to LDOWN# high 15 seconds
tLDOWN LDOWN# low duration 4 Cycles of UCLK or LCLK

The S-LINK Interface Specification - 27 MARCH 1997

[Next] [Previous] [Up] [Top]

Symbol	Description	Min	Max	Units
tRL	URESET# low to LDOWN# low		4	Cycles of UCLK or LCLK
tRU	URESET# high to UWEN# low	4		Cycles of UCLK or LCLK
tINIT	URESET# low to LDOWN# high		15	seconds
tLDOWN	LDOWN# low duration	4		Cycles of UCLK or LCLK