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The S-LINK Interface Specification

11.0 Revision History

First version released.

Name changed from Standard Detector Link to S-LINK.

Flow control diagram edited to show resumption of dataflow.

Keying pins position and function altered.

Keying pin technical drawing and arrangement table added.

Physical Description made a recommendation (was mandatory).

S-LINK connector position moved to adjacent P13 (was adjacent P11).

UNTD line changed to UTDO

LDOWN line added to LDC and pinout altered.

Flow control description altered to take account of buffer in LSC.

LDOWN line added to LSC and pinout altered.

Link established LED changed to not LDOWN.

Output drive currents changed to follow those in PCI Specification.

PCI connector positions removed from Technical Drawing.

Return lines made to function in test mode.

World-Wide Web pages rearranged.

Signals names made to look like those in PCI Specification e.g LDERR changed to LDERR# and UD31-0 changed to UD[31..0].

Reset procedure re-defined to include LDOWN#.

Three permissible clock rates defined and timing parameter values added.

Error Detection function altered to allow two possibilities: on a word-by-word basis or on a block basis.

References to actual Data Transfer Rate removed. This is implementation dependent.

Duty cycle of UCLK and LCLK added.

Section describing control/data bit expanded and tables added.

LDERR# goes low on control word if there is an error in the previous block even in word-by-word error reporting.

During test mode, data may still be transferred to the LSC (dependent on LFF#).

URESET# is asynchronous. Also, timing diagram expanded.

Technical drawings of CMC connectors added.

Naming convention for LSCs, LDCs, FEMBs and ROMBs established.

LDOWN# is latched when set by failure. Needs reset cycle to clear.

LRL[3..0] are set low after reset cycle.

UXOFF# defined as an asynchronous signal.

Signal description tables expanded and made more comprehensive.

UXOFF# functions during test mode if UTDO# is low but is inactive in test mode if UTDO# is high.

LDOWN# low due to failure also disables S-LINK.

Minor typographical corrections.

Correction made to screw-hole spacing in Figure 11.

LEDs added for XOFF# on the LDC and LFF# on the LSC

Front Panel defined for motherboards.

Paragraph on component height re-written (Section 5.3).

Data carrying channel defined as the forward channel.

ROMB buffer size equation added.

Test mode clears errors on start of test and end of test.

Power-up sequence defined in new sub-section.

Keying pins and holes moved in Figure 11.

Grounding considerations added for standoffs and keying pins.

Technical drawing of CMC bezel front-panel added.

UD25 and UD26 swapped on LSC pinout.

tLDOWN defined in Figure 7 and Table 12.

Data buffers cleared on leaving test mode. Also mentioned that the FEMB should not try to transfer data to the LSC during test mode.

Copyright statement added

Timing diagram for test mode at the LSC added (Figure 5).

Data waiting for transmission is cleared on entering test mode.

Recommendation on clock signal terminations added.

Made clear that LCLK is undefined if LDOWN# is low.

Reset at one end causes LDOWN# low at other and vice versa, if possible.

FEMB can transfer up to two words to LSC after LFF# goes low.

Maximum clock speed set at 40 MHz only.

The S-LINK Interface Specification - 27 MARCH 1997
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