32-bit S-LINK to 64-bit PCI interface


(Circuit number 680-1169-200)
Plug-in version: Top view, Bottom view
Integrated ODIN version: Front-view, Top view, Bottom view


The 32-bit S-LINK to 64-bit PCI interface (S32PCI64) can move data from a 32-bit S-LINK Link Destination Card to 3.3 Volt 32-bit or 64-bit PCI bus that runs at 33 MHz or 66 MHz. It is like a high-speed follow up of the Simple S-LINK to PCI interface. The S32PCI64 has a lower PCI-bus utilization and needs much less host processor control. The design is based on a PCI IP core from the company PLDApplications.
The host processor can set up the interface to receive up to fifteen S-LINK data blocks by writing to the Request FIFO the addresses where the data has to be stored and the maximum length of each data packet to be received. After this, the interface can receive this data without needing any intervention of the processor. After reception of the data, the host processor can read the S-LINK control words and the length of the data block received from the Acknowledge FIFO.

Although it was foreseen to have specific ODIN Link Destination Card logic integrated on the printed circuit board, this never has been tested. The reason is that the ODIN link design that was integrated soon will be out of date and will be superceded by the HOLA design.


The main features of the interface are:
  • highly autonomous data reception
  • reception speed independent of interrupt or polling latency
  • interrupt generation selectable on reception of one or several data blocks, link down, space available in Request FIFO and others.
  • control words stored independently from data
  • error information stored in the control words
  • programmable byte swap and 32-bit word swap
  • UXOFF# assertion: still 600 S-LINK words may be written
  • 32-bit S-LINK
  • 32-bit and 64-bit PCI bus
  • 33 MHz and 66 MHz PCI clock speed
  • 32-bit PCI-bus addressing
  • 3.3 Volt PCI signalling (the card cannot be used in 5 Volt PCI slots)

Throughput measurement including software overhead. 
Overhead graph




13 December 2000 Users Guide Ready. VHDL design started.
16 May 2001 Prototype based on S-LINK64 PCI board from Domique Gigi/CMS working. Expect preproduction prototypes available by November 2001
4 June 2001 Project presented at 12th IEEE-NPSS Real Time Conference Valencia (Spain)
30 August 2001 PCB design started
1 October 2001 PCB design finished. Six PCBs ordered. Will arrive 3 November
5 October 2001 Front panel design finished. 16 ordered
5 October 2001 Byte swap and 32-bit word swap logic added
31 October 2001 6 PCBs received. 3 will be mounted with S-LINK connector, 3 with ODIN logic
30 November 2001 Received mounted boards
21 December 2001 Three cards with S-LINK plugin connector tested and working. Cards with ODIN logic not tested.
5 January 2002 Card commercialised. CERN ordered three plug-in versions from Nowoczesna Elektronika
23 May 2002 Nowoczesna Elektronika sent off the three cards


13 December 2000 No one has yet started writing software
16 May 2001 Test software written by Markus Joos
21 December 2001 Linux user library written by Markus Joos. Source code only 10 KByte in size.
Seen on a PC blocks of 1 KB being transferred without any wait cycles.





Erik van der Bij & Stefan Haas - 30 July 2003