(Royal Holloway)


The ROB-IN will comprise a single-width PMC module containing a hardware-controlled event-fragment buffer memory and a buffer-manager processor, which will manage the use of the buffer memory pages according to data requests and trigger decisions received across the PMC's PCI interface, and furnish requested data to predetermined addresses on the PCI bus (e.g. ROB-OUT or ROB-Controller memory).

PCI version of ROB-inEvent-fragment data will be received on an S-LINK LDC interface connection from the ROD at an average rate of up to 100 MBytes/sec and written directly into "pages" of buffer memory using addresses taken from the "free-page FIFO". There will need to be some buffering between the S-LINK input and the buffer memory since each is driven by a different clock, but a long FIFO is not required. Indeed a simple "double-buffer" may suffice.

Under certain circumstances an XOFF signal back to the ROD will be generated on the S-LINK interface in order to stem the flow of data. This will automatically occur whenever the number of entries in the free-page FIFO drops below a programmable threshold, or when the ROB-IN is powered up or reset.

At the end of each page, or at the end of each event-fragment, the last address used will be written to the "used-page FIFO" along with status bits indicating whether this is the first, intermediate, or last page of the event-fragment. The address logic will then read the next value in the free-page FIFO as a base for addressing the subsequent page.

Both the START and the END of each event-fragment will be signalled on the S-LINK input (for instance by bits in a "control" word flagged by the S-LINK control/data bit). The length of pages will be adjustable in the hardware logic. Neither this nor the buffer-memory size should be unduly constrained by address-widths.




CERN - High Speed Interconnect - S-LINK
Erik van der Bij - 10 October 2000