ATLAS TileCal Read Out Driver
(Universitat de València)


The TileCal ROD crate for the 2000 and 2001 testbeam is fully based on 
commercially available components.

Both the front-end links and the read-out links are S-LINK based. 

The TileCal ROD crate for the testbeams in 2000 was based on a VME crate with general purpose processors. All of the boards in this system (processors and link cards) are commercially available. 

The ROD board receives data from the Front-End Boards (FEB) via a set of optical S-LINKs and will send the data in the standard ATLAS dataformat to the Read-out Buffers. The final ROD has a TTC interface which provides the L1ID, BCID and trigger type. Those numbers are checked against those from the incoming datastream. 

The complete TileCal readout is 256 drawers. As one ROD will take data from four drawers, in total 64 ROD modules and S-LINK outputs are needed. Following a L1 accept rate of 100 KHz, the expected bandwidth per link is 440 Mbit/sec (barrel) and 275 Mbit/sec (extended). 


2001 testbeam ROD crate (6 inputs, like in the diagram above).

In the 2001 testbeam modified ODIN LDC cards are  used that receive the data from the integrated front-end link. The ODIN cards are modified so that they can receive the data sent by the simplex protocol used on this front-end link.

2001 testbeam ROB crate. Data from the two ROD processor boards is received over the grey S-LINK cables. From here the data is sent over 100 Mbps Ethernet to a PC.

2001: The front-end link transmitter logic is integrated on the detector and does not use separate plug-in modules. The drawer is filled with digitizer cards

In the 1999 testbeam  the front-end links used in the testbeams were the commercial available FCS-LINK, which have been used already since the Those links will not withstand the radiation levels that exist in the final ATLAS.

In the 2000 testbeam the logic of a Simplex G-LINK S-LINK had been integrated as the front-end link. This link may withstand the radiation, but it does not have flow-control as the FCS-LINK had.


December 1999 Start of setup of full VME-based syste
March 2000 Ordered 2 x FCS LSC, 1 x FCS LDC, 3 x SPS, 1 x SSP, 3 x integrated FCS/PMC cards. Already have one single channel ODIN link. Juanba left project.
4 May 2000 System with two inputs working in testbeam used for commisioning the system. In July and August other testbeams will take physics data.
26 June 2000 Vicente Gonzalez is trying to see if the LArg ROD can be used for the Tilecal as well. A problem may be that the incoming 32-bit data on the LArg ROD is handled in two 16-bit parts, while the Tilecal needs it to be handled on a complete 32-bit basis.
13 July 2000 One Simplex G-LINK LDC bought
30 August 2000 Test beam with integrated Simplex G-LINK LSC did not work with V3.0 digitizer boards (was tested with V2.0 boards only). Went back to use Fibre Channel version (same as in 1999) and took succesfully data.
29 January 2001 PCB design of TM4plus1 started
8 June 2001 Two TM4plus1 modules sent to Valencia for programming. July 2001 testbeam will use again VME-based system with 6 modified ODIN LDC cards as front-end link input. ODIN modifications will be done in Chicago.
July 2001 Testbeam 2001 with 6 front-end links working



CERN - High Speed Interconnect - S-LINK
Erik van der Bij - 30 August 2001