3.0 Definitions

3.4 Signal Line Functions

The signal lines for the LSC are described in Table 1. The signal lines for the LDC are described in Table 2.

TABLE 1. Signal Descriptions for the LSC
Pin Symbol Pin Name I/O Description
UD[31..0] User Data input lines Input to S-LINK Data on these lines is transferred to the LSC on a low-to-high transition of UCLK when UWEN is low. UD[3..0] are ignored if UCTRL# is low. Synchronous with UCLK.
LFF# Link Full Flag Output from S-LINK Data shall only be written to the S-LINK when this line is high. After it goes low, up to two more words may be written. Functional when S-LINK is in test mode. Undefined when URESET# is low. Synchronous with UCLK.
URESET# User Reset line Input to S-LINK When low initiates a reset cycle. Asynchronous.
UTEST# User Test line Input to S-LINK When low switches the LSC to test mode. Causes LDOWN# to go low. Asynchronous.
UDW[1..0] User Data Width lines Input to S-LINK Define the data width the S-LINK is to be operated in. Data width codes at LSC and LDC must be the same. Sampled after a reset cycle.
UCTRL# User Control line Input to S-LINK When low indicates that the data to be transmitted is a control word. Causes UD[3..0] to be ignored. Synchronous with UCLK.
UWEN# User Write Enable Input to S-LINK When low enables data to be transferred to the S-LINK on the low-to-high transition of UCLK. Synchronous with UCLK.
UCLK User Clock Input to S-LINK Data is transferred to the S-LINK on the low-to-high transitions of UCLK when UWEN# is low. This is a free running clock.
LRL[3..0] Link Return Lines Output from S-LINK These lines reflect the state of URL[3..0] at the LDC. In the simplex version these lines are not functional. A simplex FEMB shall leave these lines unconnected. A simplex LSC shall connect these lines to GND. Asynchronous, even relative to each other.
LDOWN# Link Down Output from S-LINK When low indicates that the S-LINK is not operational. Asynchronous. Can go low due to:
- S-LINK failure; then LDOWN# is latched low until cleared by a reset cycle.
- S-LINK undergoing reset cycle, then LDOWN# goes high when reset cycle is complete.
- S-LINK in test mode, then LDOWN# goes high when test mode is ended.
The FEMB shall pull LDOWN# low if the LSC is not present or not powered up.

TABLE 2. Signal Descriptions for the LDC
Pin Symbol Pin Name I/O Description
LD[31..0] Link Data output lines Output from S-LINK Data present on these lines may be latched on the low-to-high transition of LCLK when LWEN# is low. LD[3..0] have special meanings when LCTRL# is low. Synchronous with LCLK.
UXOFF# User Transmit Off Input to S-LINK When low, signals the LSC to stop transmitting data. Functions in test mode if UTDO# is low but does not stop transmission of test pattern if UTDO# is high. Asynchronous.
In the simplex version this pin is not functional. A simplex ROMB shall pull-up this line to Vcc. A simplex LDC shall leave this line unconnected.
URESET# User Reset line Input to S-LINK When low initiates a reset cycle. Asynchronous.
UTDO# User Test Data Out Input to S-LINK When low, the received test pattern is transferred from the LDC to the ROMB during test mode. Sampled after a reset cycle.
UDW[1..0] User Data Width lines Input to S-LINK Define the data width the S-LINK is to be operated in. Data width codes at LSC and LDC must be the same. Sampled after a reset cycle.
LCTRL# Link Control line Output from S-LINK When low indicates that a control word is being transferred. Causes LD[3..0] to have a special meaning. Synchronous with LCLK.
LWEN# Link Write Enable line Output from S-LINK When low indicates that valid data will be transferred to the ROMB on the low-to-high transition of LCLK. Synchronous to LCLK.
LCLK Link Clock Output from S-LINK Data is transferred to the ROMB on each low-to-high transition of LCLK when LWEN# is low. This is a free-running clock if LDOWN# is high. If LDOWN# is low, this signal is undefined.
LDERR# Link Data Error Output from S-LINK When low indicates that a data transmission error has occurred or that a pattern error has occurred during test mode. With word-by-word error reporting, LDERR# goes low with the word in error and with the control word for that block. With block basis error reporting, LDERR# goes low only with the control word for the block containing the word with error.
URL[3..0] User Return Lines Input to S-LINK The state of these lines is sampled, transmitted back to the LSC and presented on LRL[3..0]. Asynchronous, even relative to each other.
In the simplex version these pins are not functional. A simplex ROMB shall connect these lines to GND. A simplex LDC shall leave these lines unconnected.
LDOWN# Link Down Output from S-LINK When low indicates that the S-LINK is not operational. Asynchronous. Can go low due to:
- S-LINK failure; then LDOWN# is latched low until cleared by a reset cycle.
- S-LINK undergoing reset cycle, then LDOWN# goes high when reset cycle is complete.
- S-LINK in test mode, then LDOWN# goes high when test mode is ended.
The ROMB shall pull LDOWN# low if the LDC is not present or not powered up.

The S-LINK Interface Specification - 27 MARCH 1997

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Pin Symbol	Pin Name	I/O	Description
UD[31..0]	User Data input lines	Input to S-LINK	Data on these lines is transferred to the LSC on a low-to-high transition of UCLK when UWEN is low. UD[3..0] are ignored if UCTRL# is low. Synchronous with UCLK.
LFF#	Link Full Flag	Output from S-LINK	Data shall only be written to the S-LINK when this line is high. After it goes low, up to two more words may be written. Functional when S-LINK is in test mode. Undefined when URESET# is low. Synchronous with UCLK.
URESET#	User Reset line	Input to S-LINK	When low initiates a reset cycle. Asynchronous.
UTEST#	User Test line	Input to S-LINK	When low switches the LSC to test mode. Causes LDOWN# to go low. Asynchronous.
UDW[1..0]	User Data Width lines	Input to S-LINK	Define the data width the S-LINK is to be operated in. Data width codes at LSC and LDC must be the same. Sampled after a reset cycle.
UCTRL#	User Control line	Input to S-LINK	When low indicates that the data to be transmitted is a control word. Causes UD[3..0] to be ignored. Synchronous with UCLK.
UWEN#	User Write Enable	Input to S-LINK	When low enables data to be transferred to the S-LINK on the low-to-high transition of UCLK. Synchronous with UCLK.
UCLK	User Clock	Input to S-LINK	Data is transferred to the S-LINK on the low-to-high transitions of UCLK when UWEN# is low. This is a free running clock.
LRL[3..0]	Link Return Lines	Output from S-LINK	These lines reflect the state of URL[3..0] at the LDC. In the simplex version these lines are not functional. A simplex FEMB shall leave these lines unconnected. A simplex LSC shall connect these lines to GND. Asynchronous, even relative to each other.
LDOWN#	Link Down	Output from S-LINK	When low indicates that the S-LINK is not operational. Asynchronous. Can go low due to: - S-LINK failure; then LDOWN# is latched low until cleared by a reset cycle. - S-LINK undergoing reset cycle, then LDOWN# goes high when reset cycle is complete. - S-LINK in test mode, then LDOWN# goes high when test mode is ended. The FEMB shall pull LDOWN# low if the LSC is not present or not powered up.