Realisation and Performance of IEEE1355 DS and HS Link based, High Speed Low Latency Packet Switching Networks

29/10/97


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Table of Contents

Realisation and Performance of IEEE1355 DS and HS Link based, High Speed Low Latency Packet Switching Networks

IEEE 1355 Switch Studies

Traffic Generator Board

Tested Networks

1024 Node 2-D Grid

Node Throughput for Grid, Clos and Torus

Scalability of Clos and Grid Networks

Latency for Clos Networks

Latency Distribution

Packet Transmission Overhead

ATLAS Level II: SCT Trigger

Atlas Level II Trigger Traffic

HS Link Switching System

Rcube Evaluation Platform

Link and Switch Demonstration

Author: Brian Martin

Email: Brian.Martin@cern.ch

Home Page: http://www.cern.ch/HSI/dshs/

Other information:
Presentation at the RT'97 conference, September '97, Beaune, France