The requirement to study different topologies for a large number of nodes, imposes a system design and implementation which is highly modular and flexible while maintaining a very low per node cost. This has been achieved by building the testbed from three basic modules, which are packaged in VME mechanics :
A traffic node can simultaneously send and receive data at the full
link speed of 100 Mbits/s. A series of packet descriptors is used
to define the traffic pattern. The packet destination address, the
packet length and the time to wait before dispatching the next packet
is programmable. Each traffic node has memory for up to 8k such packet
descriptors. The dispatch algorithm is implemented in an FPGA
which can be reconfigured under host control. A control processor
is used to supervise the operation of a group of 4 traffic nodes.
To reduce the number of external connections, sixteen traffic nodes are connected directly to an on board STC104 packet switch. The remaining 16 ports of the switch are brought out to the front panel for inter module connections. Boards can be interconnected either directly, or via switch units which contain one STC104 with all 32 ports brought out to the front panel.
To measure latency, the timing nodes transmit and analyse time stamped packets which cross the network between chosen points. The same modules can also be inserted into any cabled connection to provide a snapshot of the traffic passing through that point. This can provide debugging information and additional data on congestion "hot spots".
A VME crate contains 128 traffic nodes and the entire 1024 node system
can be housed within eight crates. All crates have an Ethernet port
which drives an OS-link daisy chain connection to the control processors. The STC104 packet
switches are configured via a separate DS control network which is
independent from the main data path. Further details on the design
of the testbed have been presented in [8].