IEEE 1355 DS links are bidirectional flow-controlled point-to-point
serial links running at 100 Mbaud. DS link networks can be
built using the 32 port SGS Thompson C104 packet
switch[17]. This chip uses wormhole routing to route DS
link packets; preloaded routing tables determine the packet's
destination port on the basis of the packet header, as soon as this
header has been received by the source port. The C104 does
not use a bus based architecture, instead a non-blocking
crossbar is implemented to route packets. It has a switching latency
of 1 
s.
As part of the Macramé Esprit project, CERN has constructed a very
large network testbed[21] based on DS links and C104
switches. This has allowed the investigation of latency and
throughput for many different traffic patterns and network
topologies up to 1024 terminal-nodes. The Macramé network has
demonstrated that large DS link networks can be built, that they
scale very well, and that these networks can cope with the high data
rates required for the ATLAS experiment[5]. Furthermore,
it has proven that the per-link flow control, together with well
designed hardware[13], can result in very reliable
systems: a maximum Bit Error Rate (BER) of 
[21] has been reported.