Spokesman: S. Cittolin
In conjunction with RD27, RD12 is developing a multi-function optoelectronic distribution system [5,6,7] which has the potential to meet the requirements of all the proposed subdetectors of the LHC experiments. The implementation of a common solution to this problem would result in economies of scale and result in a rationalization of the development, operational and support efforts required.
The RD12/RD27 system is based on the use of a few relatively high power laser sources which distribute the signals via entirely passive all-glass networks composed of a hierarchy of optical tree couplers. The couplers have small size, low mass and unlimited bandwidth, require no power and are potentially highly reliable, while the single-source architecture allows the laser to be well protected and easily upgraded as technology progresses. The laser operates at 1310 nm, at which the chromatic dispersion of the fibre is negligible.
It has been shown that it is possible to time-division multiplex and encode the first-level trigger decisions, broadcast commands and individually addressed controls and data for optical transmission to several thousand front-end electronics destinations per transmitter. (Successful operation has been demonstrated through three levels of 1:32 couplers, corresponding to an optical fanout of 1:32768).
The ‘prompt’ TDM A-channel which is dedicated to the broadcasting of the first-level trigger-accept signal has been designed for low latency. The total delay from the trigger-accept input from the central trigger processor to the output from the timing receiver is less than 2 bunch-crossing intervals plus one bunch-crossing interval per 5m of optical fibre in the distribution path. The bunch-crossing timing reference can be recovered from the received encoded data stream with a time jitter of 50 - 200 ps rms (depending on the optical fanout), comparable with the spread in event origin time due to the LHC bunch collision length and expected longitudinal phase modulation of the circulating beams.
These facilities can be implemented with the relatively low transmission rate of 160.32 MBaud, permitting the use of InGaAs photodetectors manufactured in increasingly large volume for the expanding Sonet OC-3 telecommunications market. Extensive deployment plans for fibre in Europe and the USA suggest that these components will become available at affordable cost during the time frame of LHC preparation, and industrial collaboration is in progress for the development of sub-miniature optical fibre connectors and device packaging.
The development of a single-crate transmitter subsystem has been completed and a small series production is in progress for the first users. The subsystem comprises the clock generator and receiver, 160.32 MHz VCXO/PLL, TDM biphase mark encoder, laser transmitter, thermoelectric cooler and laser diode controllers, protection system, RF modulator, 1:32 root coupler and a test module. External VMEbus B- channel serializer and master phase modules are currently being developed. A lower cost mini-system has also been produced which generates compatible signals for front-end electronics development and integration work.
The architecture of an associated timing receiver ASIC has been defined and its design is being undertaken by CERN ECP Microelectronics Group in conjunction with Padova University/INFN. This chip, which will be required in large quantities, accepts a single input from the photodetector and generates a full range of decoded and deskewed signals for front-end electronics controllers. The ASIC comprises an analog part (including the postamplifier, AGC circuits and clock recovery/fine deskew PLL) and a digital part (including the decoding, demultiplexing, coarse deskew and command processing sections).
Technology evaluation chips including alternative implementations of basic elements of the analog part are currently being fabricated, while the digital part has been simulated and an FPGA implementation will be tested before proceeding to custom silicon. It is anticipated that hybrid timing receivers will be available early in 1995 while a fully integrated timing receiver ASIC should be completed about 9 months later.
A VME-based Fast Dual Port Memory (FDPM) [8] has been designed and 15 modules have been produced in versions with ALTERA and MAG control logic [9]. They are used in several R& D projects and by external laboratories. The modules, which allow up to 400MB/s input-output from a 512 MB static memory, are mainly used as test tools to generate and acquire data in front-end digital systems such as ADCs, digital filters and fast data links.
The continuation of this study is the design of a more advanced unit able to support the full data acquisition functions required in an LHC experiment, in order to implement the front-end readout and to generate and collect data in an event builder switch-based system. The new design consists of a 100 MB/s two-port memory of 2MB, expandable up to 100MB, with microprogrammable sequencers to read out front-end electronics and to drive a fast output data link.
The unit behaves as a disk controller operating at an event rate of up to 100 kHz, with the capability of opening/writing/closing files (event buffer) and opening/reading/deleting files under the control of external command signals. The memory control may be implemented by hardwired logic or by embedded processors (both ways are being studied). The exploitation of standard buses, such as PCI, for peripheral interconnections is also being pursued. A Fibre Channel (FC) interface to connect the memory output to a switch port is under construction. The protocol generation is entirely hardwired in order to communicate with a commercial FC switch at the maximum speed.
To perform the filter optimization a design tool called FIROSMIN has been created (the software is available on the CERN caeftp server). The applied method is ‘design by training’, where the filter parameters are found by minimizing the mean squared error (MSE) between the filter output and the desired output. The procedure is very similar to the learning process of neural networks, but the operator derived is a digital filter with a predefined structure. Adaptive filtering has a common optimization strategy but the adaptation is performed during operation whereas the training is performed prior to operation. Thus adaptive filters can adapt to changing conditions in real-time but they have the drawback of being computationally intensive. The training method is especially suitable for cases where the specifications are given in the time domain and not in the frequency domain, and for adaptive non-linear hybrid filters which are difficult to design using the analytical approach.
Stochastic algorithms offer an alternative to gradient-based optimization. To investigate their utilization the SAFIR tool, incorporating simulated annealing as the optimization algorithm, was developed. The tool also includes a VHDL output generator to test the designed filters in a Xilinx environment.
For signal base line estimation a set of sparse nonlinear filters has been developed. As the signal pulses can be considered as outliers, linear operators like moving average give a strongly biased estimate [11]. Non-linear filters perform better, producing a totally unbiased base line estimate when a sufficient window size is used. In order to overcome the problem of sorting a large number of samples, sparse structures are used: the input is obtained by downsampling the original set. The sparse filters evaluated include the OS filter, the L-filter and the Ll-filter [13,14]. The operators were optimized using the training approach.
Filter structures have been implemented in hardware as part of the FERMI readout microsystem (RD16). Some algorithms have been tested using the DataWave processor simulator developed by ITT Intermetall. DataWave is a single-chip multiprocessor system, originally designed for image processing tasks in digital television applications. Each processor cell is an autonomous RISC with local program and data stores. Due to the high level of parallelism and the optimized instruction set the DataWave processor achieves a maximum performance of 4 GOPS [12,19].
Another application of video industry developments to LHC trigger and front-end digital systems is being studied in a collaboration between LPNHE-X and Philips. The design of a circuit composed of 16 parallel 16-bit integer DSPs running at 40 MHz in pipeline mode has been completed. LPNHE-X is responsible for the data communication part, the DSP software development and the prototype tests which were started in July 1994. The study will continue with the completion of the VHDL description of the chip behaviour and the conception and realisation of VME boards with multiple L-Neuro chips for applications to calorimeter signal and level-1 trigger processing.
In Padova the Memory Address Generator (MAG) circuit has been produced using CMOS 1.2 µm technology and integrated in the FDPM modules. It allows programmable address generation at a rate of 100 MHz. A switching capacitor CMOS discriminator [35] suitable for LHC instrumentation has been designed and 1.2 µm CMOS prototypes tested. It runs at 66 MHz with 10 mV threshold and 20 mW power dissipation. The design is the building block for front-end ADCs.
The set of virtual instruments developed by RD12 supports CAMAC and VMEbus systems, accessed by MacVEE or CES and NI-MXI interfaces, as well as histogram, data acquisition and filter design libraries [28,29,30]. The LabVIEW packages and documentation are available by FTP: Machine caeftp, Login anonymous, Password e-mail address, Access /home/ftp/labview/CERN.LIB/.