HYTEC HTIP-800 Source & Destination Units

TURBOchannel to HIPPI Interface
HIPPI to TURBOchannel Interface

High-Speed parallel interconnect for DEC workstations

The HTIP-800 S & D are the first family of HIPPI Interfaces. The S unit is a Source (Tx) and the D unit is a Destination (Rx). Each unit plugs into a single TURBOchannel slot inside DEC TURBOchannel Workstations.

The HIPPI protocol (High Performance Parallel Interface) is an open standard specifying a high speed communication mechanism (100 MBytes/sec) based on low cost, a single multiway twisted pair cable. The speed of the 32 bit parallel connection and simplicity of the protocol make the HIPPI bus the ideal outside world companion to the TURBOchannel. The units come complete with software drivers written in C (source provided) for the OSF1 and ULTRIX operating systems, which give point to point communication. Workstation to Workstation sustained transfers rates at over 700Mbits/sec can be achieved. Transfer rates of over 850Mbits/sec have been maintained into the destination unit over distances of up to 25 meters.

These units are the product of a joint design collaboration between the CERN organisation and Digital Equipment Corporation. They are manufactured and tested by Hytec Electronics and are currently working on the NA48 data acquisition system at CERN.

Features

• HIPPI Source or Destination, in a single TURBOchannel slot.
• Source or Destination units may be purchased singularly or in pairs.
• Standard HIPPI signals, standard connector and standard protocol.
• Fully compatible with Alpha AXP TURBOchannel workstations and servers running OSF1.
• Sustained peer to peer transfers at <700Mbits/sec at up to 25 meters, 850Mbits/sec into destination units.
• Software drivers, with source code, for OSF1 or ULTRIX included.
• Device Driver and User Level Library for easy programming.
• Fully compatible with the TURBOchannl DECstation 5000 range.
• High speed DMA: on board scatter gather map for DMA operation.
• 64 map entries for user's buffers (up to 512 MB on Alpha AXP).
• History memory: a 32K x 40 bits RAM records transmission errors and protocol information.
• Register file: Read/Write configuration register, status information and interrupt processing register.
• Full TURBOchannel compliant ROM with ident and self-test code.

Documentation

Complete user documentation of the hardware interfaces is included in the package. This will allow custom drivers to be written for optimised performance for specific applications.

Future Hardware

There will be versions of both units to work with the PCIbus interface, which will in time replace the TURBOchannel and will become an industry standard.

Future Software

Implementation of TCPIP protocols. This would allow the interfaces to be used for high speed interconnection of existing services (eg file sharing with NSF, remote login with TENET, etc). In a typical configuration the HIPPI interface will be connected to a HIPPI switch, to form a network. Farms of workstations could be interconnected to give low cost very high performance supercomputing systems.

For further information and worldwide agents, contact:

HYTEC ELECTRONICS LIMITED

5 Cradock Road, Reading, Berkshire, RG2 OJT, UK

Tel.: 44 (0) 734 757770

Fax: 44 (0) 734 757566

E-mail: email@hytecw.uucp

This is one of the CERN High Speed Interconnect pages - 3 Juny 1995 - Arie van Praag