Global Data
Used Packages
IEEE.Std_Logic_1164
Interface
-- ==============================================================================
-- ==============================================================================
-- ---------------------------------------------------------------------------
-- All signals of the ICs are shown in the port description.
-- The order of signals is according to the specifications of the
-- S-LINK and TYLK2501.
--
-- Signals that should be driven directly on the board are shown as
-- comment with the word 'direct'.
-- ---------------------------------------------------------------------------
-- Total I/O signals (including clock pins, excl. test port) (85)
-- ---------------------------------------------------------------------------
-- S-LINK signals (43)
-- ---------------------------------------------------------------------------
UD : in std_logic_vector (31 downto 0);
URESET_N : in std_logic ;
UTEST_N : in std_logic ;
UCTRL_N : in std_logic ;
UWEN_N : in std_logic ;
UCLK : in std_logic ;
LFF_N : out std_logic ;
LRL : out std_logic_vector (3 downto 0);
LDOWN_N : out std_logic ;
UDW : in std_logic_vector (1 downto 0); -- for future use, grounded
-- ---------------------------------------------------------------------------
-- S-LINK LEDs ( 4)
-- ---------------------------------------------------------------------------
-- POWERLED_N : direct -- Green LED between Vcc and Gnd with R
TESTLED_N : out std_logic ; -- Red
LUPLED_N : out std_logic ; -- Green
LFFLED_N : out std_logic ; -- Red
ACTLED_N : out std_logic ; -- Green. Activity LED.Data being sent
-- ---------------------------------------------------------------------------
-- Special signals ( 1)
-- ---------------------------------------------------------------------------
XCLK : in std_logic ; -- 125 MHz external clock
-- ---------------------------------------------------------------------------
-- Serializer/Deserializer (TLK-2501) -- general terminals ( 1)
-- ---------------------------------------------------------------------------
ENABLE : out std_logic ;
-- GND : direct -- to Gnd
-- GNDA : direct -- to Gnd
-- LOCKREFN : direct -- to Vcc
-- LOOPEN : direct -- to Gnd. Loop enable. High for
-- Internal loopback path active.
-- PRBSEN : direct -- to Gnd.
-- RREF : direct -- to an external reference resistor,
-- used to provide an accurate current
-- reference to the transmitter
-- and receiver I/O circuitry.
-- TESTEN : direct -- Unconnected
-- ---------------------------------------------------------------------------
-- Transmitter side of TLK-2501 -- used for data transmission (18)
-- ---------------------------------------------------------------------------
-- Differential serial outputs to physical link
-- DOUTTXN : direct -- negative terminal of the differential
-- serial output
-- DOUTTXP : direct -- positive terminal of the differential
-- serial output
-- GTX_CLK : direct -- reference clock to transmitter
-- interface. Same connection as XCLK
TXD : out std_logic_vector (15 downto 0);
-- Terminals to control the kind of data presented to the TLK-2501
-- and their validity
TX_EN : out std_logic ;
TX_ER : out std_logic ;
-- ---------------------------------------------------------------------------
-- Receiver side of TLK-2501 -- return lines and flow control (19)
-- ---------------------------------------------------------------------------
-- Differential serial inputs from the forward channel
-- DINRXN : direct -- negative terminal of the differential
-- serial input
-- DINRXP : direct -- positive terminal of the differential
-- serial input
RXD : in std_logic_vector (15 downto 0);
-- Received parallel data
RX_CLK : in std_logic ; -- Recovered clock.
-- Terminals to control the kind of data received from TLK-2501
-- and their validity
RX_ER : in std_logic ;
RX_DV : in std_logic ;
ICLK_2 : in std_logic ;
Local Signals
--------------------------------------------------------------------------------
-- signal names have where possible prefix of module where it is output from
-- signal names have where possible suffix of clock they are synchronised to
-- U : Synchronous to UCLK
-- X : Synchronous to XCLK
-- I : Synchronous to ICLK_2
-- RX : Synchronous to RX_CLK
--------------------------------------------------------------------------------
signal REG_UTEST_U : std_logic ;
signal REG_UCTRL_N_U : std_logic ;
signal REG_UWEN_N_U : std_logic ;
signal REG_UTEST_N_I : std_logic ;
signal REG_URESET_N_I: std_logic ;
signal REG_UD_U : std_logic_vector (31 downto 0) ;
signal TEST_TMODE_N_U: std_logic ;
signal TEST_DATA_U : std_logic_vector (33 downto 0) ;
signal FIFO_FULL_U : std_logic ;
signal FIFO_DATA_I : std_logic_vector (33 downto 0) ;
signal FIFO_EF_I : std_logic ;
signal FIFO_WREF_U : std_logic ;
signal FRAME_RE_I : std_logic ;
signal FRAME_DATA_I : std_logic_vector (31 downto 0) ;
signal FRAME_CMD_I : std_logic_vector (2 downto 0) ;
signal PAR_DATA_I : std_logic_vector (31 downto 0) ;
signal PAR_TXCMD_I : std_logic_vector (2 downto 0) ;
signal CRC_COMMAND_I : std_logic_vector (2 downto 0) ;
signal CRC_DATA_I : std_logic_vector (31 downto 0) ;
signal RCH_XOFF_RX : std_logic ;
signal RCH_LDOWN_RX : std_logic ;
signal RCH_LDC_RESET_RX : std_logic ;
signal RCH_RXER_RX : std_logic ;
signal RCH_TESTER_RX : std_logic ;
signal CTRL_RESET_I : std_logic ;
signal CTRL_LDCRESET_I : std_logic ;
signal CTRL_LDOWN_I : std_logic ;