entity core_odinldc is
generic(NUMBEROFRX: integer := 2;    -- 1: single g-link receiver 
                                     -- 2: double g-link receiver
        DIV0      : integer := 1;    -- 0: single or double version at 64 MHz
                                     -- 1: double version at 40 MHz
        INVERTLCLK: boolean := TRUE  -- TRUE: LCLK output is inverted one of
                                     -- the one used for the output registers.
port (
-- S-LINK signals                                                       (46)
   LD            : out std_logic_vector(31 downto 0);
   LCTRL_N       : out std_logic;
   LWEN_N        : out std_logic;
   LCLK          : out std_logic; ...
-- S-LINK LEDs                                                          ( 4)
-- Transmitter G-LINK (HDMP-1032) -- return lines and flow control      (22)
   TXA_DATA      : out std_logic;
   TXA_CNTL      : out std_logic;
   TXA_D         : out std_logic_vector(15 downto 0); ...
-- Receiver G-LINK    (HDMP-1034) -- used for data reception      (24 or 45)
   RX_DATA        : in  std_logic_vector(NUMBEROFRX downto 1);
   RX_CNTL        : in  std_logic_vector(NUMBEROFRX downto 1);
   RX_D           : in  std_logic_vector((NUMBEROFRX*16)-1 downto 0);  ...
end core_odinldc;


For designers who like to integrate the logic of an ODIN-type S-LINK, the protocol logic is made available as an Intellectual Property Core. This core can then be integrated with other logic on the ROD or ROB, which has many advantages: The ODIN core is fully written in device independent VHDL code, which makes that it may be implemented in a variety of FPGAs (Altera, Xilinx,...). Reference schematic diagrams and design support is available. A link implemented with the core is fully compatible with the ODIN Link Cards in the plug-in version.

Examples of FPGA resource requirements

Single LSC
Double LSC Single LDC Double LDC
Altera 10K30A LCELLs
726 (42%)
1006 (58%)
Xilinx xc4028xl CLBs
382 (37%)
Xilinx xc4052xla,-09 CLBs  
515 (26%)
538 (27%)

The ODIN interface is a standard S-LINK implementation, which uses in the full configuration two 3.3 V Hewlett Packard G-LINKs (HDMP-1032/1034) as a physical layer for the forward channel. The same chip is used for the return channel. For the optical transmission small form-factor (SFF) optical transceivers are used. There are two versions of the card: one with a single fibre for the forward channel and one that uses two optical fibres. These can transfer data at 128 MB/s and 160 MB/s respectively.


Single channel version
Double channel version
32 MHz
40 MHz
Maximum data transfer rate
128 MB/s
160 MB/s
Maximum control word transfer rate
64 MB/s
80 MB/s
Sampling rate return lines
8 MHz
5 MHz
Max. 1 m fibre length difference


3 October 2000 IP Core design for single LDC ready
27 October 2000 Same core parametrisable for single and double version LDC, not debugged yet
20 April 2000 Single and double LDC tested. Added extra generic for DIV0. Work started on making core for LSC.



Note that there is a copyright statement in the core, which states that
you need to request a licence if you want to use it for commercial purposes.
Please contact us for additional information.

To guarantee a sucessful integration of the core,
ask Erik van der Bij for a review of your schematic and PCB design

CERN - High Speed Interconnect - S-LINK
Erik van der Bij - 16 May 2001