MACHINE 1 - STATE FORMAT SPECIFICATION State Acquisition Mode 100 MHz/1M State Master Clock: J^ Clock Inputs Pod D4 Pod D3 TTL TTL D Label Pol MLKJ 15 ... 87 .... 0 15 ... 87 .... 0 UD + ................ ................ **************** LRL + ................ ................ ................ UDW + ................ ................ ................ UCTRL_ + ................ ................ ................ UWEN_ + ................ ................ ................ UTEST_ + ................ ................ ................ URSET_ + ................ ................ ................ LDOWN_ + ................ ................ ................ LFF_ + ................ ................ ................ UCLK + ................ ................ ................ FPAFF_ + ................ ................ ................ DVAL_ + ................ ................ ................