Simple S-LINK to PMC interface
ROMB-D-40-x-5.0-130
(Circuit no. 680-1110-200)
Bottom side of S-LINK to PMC interface with PMC connectors.
The S-LINK connector is mounted at the
other side of the card.
DESCRIPTION
The Simple S-LINK to PMC (SSP) interface is a PCI Mezzanine Card that is
needed to interface S-LINK Link Destination Cards (LDCs) in a PMC environment.
The interface itself is fully compliant to the PMC as well as the S-LINK
specification. However, when the S-LINK LDC is plugged onto the SSP, the
total height will be larger than allowed by the PMC specification.
The interface was made with simplicity of design in mind. This has consequences
for the ease of programming only. With the integrated DMA, the board can
transfer data at the full PMC bus speed which is theoretically 130 MByte/sec.
The Simple S-LINK to PMC has Read-out Motherboard (ROMB) functionality,
is a duplex implementation, which can handle an LCLK with a frequency up
to 40 MHz, having 5 Volt signal levels and a maximum transfer rate of 130
MByte/sec. In S-LINK terms this is coded as a ROMB-D-40-x-5.0-130.
Furthermore the interface features:
-
Buffer size of 256 words
-
UXOFF# active after 128 words received and not read out
-
Programmable UDW[1..0], URESET# and UTDO# lines
-
Programmable URL[3..0] lines
-
Readable LDOWN#, LDERR# and LCTRL# lines
-
Interrupt on change of status of LDOWN#, LDERR# or LCTRL#
As far as the PMC interface goes it features:
-
33 MHz PCI clock
-
32-bit databus
-
Integrated DMA
-
Bus target and initiator functionality
STATUS
Hardware
-
1/96: prototype built in wire-wrap
-
14/2/96: prototype tested
-
18/6/96: 2 PCBs passed first tests, wait for test software before testing
other 3 boards
-
30/10/96: Another 5 PCBs are mounted and being tested.
-
18/2/97: Boards available from INCAA
Computers
-
10/7/97: INCAA Computers starts
second production run
-
10/7/97: testing upgrade which will give board full speed PCI capability
while keeping fully compatible with old software. Only two PALs need to
be replaced.
-
23/7/97: testing of 'Gold' version (full speed PCI) finished. Observed
78 MByte/sec on RIO2.
Software
-
28/2/96: test software is being written
-
28/2/96: LynxOS driver being written
-
18/6/96: first version of test software running
-
30/10/96: newer versions of test software on web, ATLAS software being
written
-
18/2/97: ATLAS library ready
-
10/8/98: Drivers for Linux, LynxOS and NT available
-
9/9/98: Driver for VxWorks in development at Saclay
DOCUMENTATION
CONTACTS
CERN - High
Speed Interconnect - S-LINK
Erik van der Bij - 12 May
2000