" ========================================================================== " " File name: slitest.abl " Title : SLITEST PAL (680-1110-350) " Purpose : Reset generator and error counter for SLITEST " " Authors : James Rouet CERN, ECP division " Erik van der Bij CERN, ECP division " " Notes : - Pinout for PLCC28 package " - Same PAL used 3 times on SLITEST " 1. Checkctrl=0, LD=Vcc (checks errors in datawords) " 2. Checkctrl=1, LD=LD[0] (checks dataword error in ctl word) " 3. Checkctrl=1, LD=LD[1] (checks ctlword error in ctl word) " " " ========================================================================== "| Version | Author | Mod. Date | Change Made | " -------------------------------------------------------------------------- "| 0.0 | RJ | 10- 6-96 | First PLCC28 version | "| 0.1 | EB/RJ | 9- 7-96 | Added counter | "| 0.2 | EB | 11- 7-96 | Overflow, test vectors Checksum: E182 | "| 0.3 | EB | 18- 7-96 | Reset or test input Checksum: E6CC | " ========================================================================== Module SLITEST Title 'Reset generator and error counter for SLITEST' SLITEST device 'P22V10C'; " ========================================================================== " INPUTS " ========================================================================== Declarations SLICLK pin 2; " SLIDAD/SLIDAS clock RSTCHIP_n pin 3; " 0: chip for reset state machine " 1: chip for test state machine LDOWN_n pin 4; " Link down from S-LINK " Manual button for reset (or test) cards BUTTONH pin 5; " Contact high when pressed BUTTONL pin 6; " Contact low when pressed RSTCTR_n pin 7; " Reset counter LCTRL_n pin 9; " Link Control from S-LINK LDERR_n pin 10; " Link Error from S-LINK LD pin 11; " Count only if LD is 1 CHECKCTRL pin 12; " Count errors in CTRL words if 1 LWEN_n pin 13; " Link Write Enable " ========================================================================== " OUTPUTS " ========================================================================== URESET_n pin 27 istype 'reg_D, invert'; " Mixed System Reset UTEST_n pin 17 istype 'reg_D, invert'; " Temporary signal for SM " use also for utest# if " rstchip_n=1 CT7 pin 18 istype 'reg_D, invert'; " Bit 7 is overflow CT6 pin 21 istype 'reg_D, invert'; " Error counter bits CT5 pin 23 istype 'reg_D, invert'; " active low outputs CT4 pin 24 istype 'reg_D, invert'; " Counts to 128 CT3 pin 20 istype 'reg_D, invert'; CT2 pin 19 istype 'reg_D, invert'; CT1 pin 25 istype 'reg_D, invert'; CT0 pin 26 istype 'reg_D, invert'; " ========================================================================== " DECLARATIONS " ========================================================================== H, L, C, X, Z, P = 1, 0, .C., .X., .Z., .P.; Counter = [CT7,CT6,CT5,CT4,CT3,CT2,CT1,CT0]; StReg = [URESET_n, UTEST_n]; Idle = [ 1 , 1 ]; " Power on state WaitLD0 = [ 0 , 1 ]; WaitLD1 = [ 0 , 0 ]; WaitBt1 = [ 1 , 0 ]; " ========================================================================== " EQUATIONS " ========================================================================== Equations StReg.C = SLICLK; Counter.C = SLICLK; " Count when " 1. Checking datawords: just count errors. " LD should be pulled high, reduces amount of product terms " 2. Checking control words: count errors and check databit " 1 or 0 to see if it was error in control or data word when !RSTCTR_n " Can't use .ar as will reset also state then Counter.d := 0; " machine (.ar shared by all flip-flops) else when ( (!LWEN_n & !CHECKCTRL & LCTRL_n & !LDERR_n & LD & !CT7.q) # (!LWEN_n & CHECKCTRL & !LCTRL_n & !LDERR_n & LD & !CT7.q)) then Counter.d := Counter.q + 1; else Counter.d := Counter.q; " ========================================================================== " STATE DIAGRAM " ========================================================================== State_Diagram StReg; " State machine operates for reset if RSTCHIP_n=0. Connect URESET_n " State machine operates for utest# if RSTCHIP=1 (basically skips waiting " for LDOWN_n. Connect UTEST_n state Idle: " Power on state if (BUTTONH & !BUTTONL) then WaitLD0 " Wait for reset button pressed else Idle; state WaitLD0: " Give out reset to card if (!LDOWN_n # RSTCHIP_n) then WaitLD1 " Wait until reset is seen by card else WaitLD0; state WaitLD1: if ( LDOWN_n # RSTCHIP_n) then WaitBt1 " Wait until card comes out of reset else WaitLD1; state WaitBt1: " Remove reset if (!BUTTONH & BUTTONL) then Idle " Wait until reset button released else WaitBt1; " ========================================================================== " TEST VECTORS " ========================================================================== Test_vectors 'RESET STATE MACHINE' "================================= ([SLICLK, RSTCHIP_n, LDOWN_n, BUTTONH, BUTTONL] -> [StReg]) [ 0 , X , X , X , X ] -> [Idle ]; [ C , 0 , X , 0 , 1 ] -> [Idle ]; "not pressed [ C , 0 , X , 1 , 1 ] -> [Idle ]; " Test debouncing [ C , 0 , X , 0 , 0 ] -> [Idle ]; [ C , 0 , X , 1 , 0 ] -> [WaitLD0]; [ C , 0 , 1 , X , X ] -> [WaitLD0]; [ C , 0 , 0 , X , X ] -> [WaitLD1]; [ C , 0 , 0 , X , X ] -> [WaitLD1]; [ C , 0 , 1 , X , X ] -> [WaitBt1]; [ C , 0 , X , 1 , 0 ] -> [WaitBt1]; " still pressed [ C , 0 , X , 1 , 1 ] -> [WaitBt1]; " Test debouncing [ C , 0 , X , 0 , 0 ] -> [WaitBt1]; [ C , 0 , X , 0 , 1 ] -> [Idle ]; Test_vectors 'UTEST# STATE MACHINE' "================================= ([SLICLK, RSTCHIP_n, LDOWN_n, BUTTONH, BUTTONL] -> [StReg]) [ 0 , X , X , X , X ] -> [Idle ]; [ C , 1 , X , 0 , 1 ] -> [Idle ]; "not pressed [ C , 1 , X , 1 , 1 ] -> [Idle ]; " Test debouncing [ C , 1 , X , 0 , 0 ] -> [Idle ]; [ C , 1 , X , 1 , 0 ] -> [WaitLD0]; " continues indep [ C , 1 , X , X , X ] -> [WaitLD1]; " of LDOWN# [ C , 1 , X , X , X ] -> [WaitBt1]; [ C , 1 , X , 1 , 0 ] -> [WaitBt1]; " still pressed [ C , 1 , X , 1 , 1 ] -> [WaitBt1]; " Test debouncing [ C , 1 , X , 0 , 0 ] -> [WaitBt1]; [ C , 1 , X , 0 , 1 ] -> [Idle ]; Test_vectors 'ERROR COUNTER' "=========================== ([SLICLK, RSTCTR_n, LWEN_n, LCTRL_n, CHECKCTRL, LDERR_n, LD] -> [Counter]) [ 0 , 1 , X , X , X , X , X] -> [255]; [ C , 1 , 0 , 0 , 1 , 0 , 1] -> [254]; [ C , 1 , 0 , 0 , 1 , 1 , 1] -> [254]; [ C , 0 , 0 , 0 , 1 , 0 , 1] -> [255];"rst Test_vectors 'ERROR COUNTER: CONTROL WORDS' "========================================== ([SLICLK, RSTCTR_n, LWEN_n, LCTRL_n, CHECKCTRL, LDERR_n, LD] -> [Counter]) [ C , 0 , 0 , 0 , 1 , 0 , 1] -> [255];"rst " Don't count if no WEN [ C , 1 , 1 , 0 , 1 , 0 , 1] -> [255]; " Don't count if no error [ C , 1 , 0 , 0 , 1 , 1 , 1] -> [255]; " Don't count if no control word [ C , 1 , 0 , 1 , 1 , 0 , 1] -> [255]; " Don't count if no databit set [ C , 1 , 0 , 1 , 1 , 0 , 0] -> [255]; " But do if everything is fine [ C , 1 , 0 , 0 , 1 , 0 , 1] -> [254]; Test_vectors 'ERROR COUNTER: DATA WORDS' "======================================= ([SLICLK, RSTCTR_n, LWEN_n, LCTRL_n, CHECKCTRL, LDERR_n, LD] -> [Counter]) [ C , 0 , 0 , 1 , 0 , 0 , 1] -> [255];"rst " Don't count if no WEN [ C , 1 , 1 , 1 , 0 , 0 , 1] -> [255]; " Don't count if no error [ C , 1 , 0 , 1 , 0 , 1 , 1] -> [255]; " Don't count if no data word [ C , 1 , 0 , 0 , 0 , 0 , 1] -> [255]; " But do if everything is fine [ C , 1 , 0 , 1 , 0 , 0 , 1] -> [254]; Test_vectors 'ERROR COUNTER: CONTROL WORDS COUNT TO OVERFLOW' "============================================================ ([SLICLK, RSTCTR_n, LWEN_n, LCTRL_n, CHECKCTRL, LDERR_n, LD] -> [Counter]) [ C , 0 , 0 , 1 , 0 , 0 , 1] -> [255];"rst @CONST CTUP=254; @repeat 128 { [ C , 1 , 0 , 0 , 1 , 0 , 1] -> [CTUP]; @CONST CTUP=CTUP-1; } " See if sticks at overflow (only one LED on) [ C , 1 , 0 , 0 , 1 , 1 , 1] -> [127]; [ C , 1 , 0 , 0 , 1 , 1 , 1] -> [127]; Test_vectors 'ERROR COUNTER: DATA WORDS COUNT TO OVERFLOW' "========================================================= ([SLICLK, RSTCTR_n, LWEN_n, LCTRL_n, CHECKCTRL, LDERR_n, LD] -> [Counter]) " Count errors in data words [ C , 0 , 0 , 0 , 1 , 0 , 1] -> [255];"rst @CONST CTUP=254; @repeat 128 { [ C , 1 , 0 , 1 , 0 , 0 , 1] -> [CTUP]; @CONST CTUP=CTUP-1; } " See if sticks at overflow (only one LED on) [ C , 1 , 0 , 0 , 1 , 1 , 1] -> [127]; [ C , 1 , 0 , 0 , 1 , 1 , 1] -> [127]; End " ========================================================================== " END OF FILE " ==========================================================================