TM4plus1

Active S-LINK to VME64x transition module


(Circuit number 680-1169-150)

DESCRIPTION

The active S-LINK to VME64x board (TM4plus1) is a VME64x transition module that has slots for four S-LINK link cards and has an integrated ODIN Link Source Card. The S-LINK slots can fitted with any type of Link Destination Card. The transition module fits on the backside of the new VME64 Extensions crates. It will be used whenever I/O has to be connected to the back of a crate. Notably the ATLAS Read-out Driver and Read-out Buffer devices can make use of this transition module. 

The board has been designed to enable the ATLAS Tilecal detector to use the ATLAS LArg Read-Out Driver.

The VME64 Extensions crate uses 5-row connectors for P1 and P2, while P3 is freely definable. For this application, also for P3 a 5-row connector is chosen.
The S-LINK team has developed a P3 backplane which has exactly the same pinout as P2. On one 5-row connector, two sets of S-LINK signals are mapped; the top half of the connector are for one S-LINK, while the bottom half is used for the other one. The S-LINK signals are on the outer four rows, which feed directly through to the board that is inserted at the front-side of the crate. The middle row of the connector is only used to receive power from, while the signal pins on this middle row are bused and can be user defined.

The S-LINK pin mapping has been designed for having low cross-talk and high signal quality. E.g. the clock lines are surrounded by ground pins and the signal lines need a minimal amount of crossings between the S-LINK and P2/P3 connectors. The S2VME64x is completely passive. It has series resistors in the signal lines to improve the signal quality. The S2VME64x is powered via the P2 connector and P3 connectors. 

The transtion module features:

  • 9U x 16 cm form factor
  • Four slots for LDC cards
  • One integrated ODIN LSC (128 or 160 MB/s)
  • Power taken from P2 and P3 connectors (5 Volt or 3.3 Volt)
  • 3.3 Volt supply to the link cards (regulator on the transition module)
  • 4 KWord buffer for each LDC slot (UXOFF active after 3 KWord received)
  • Altera 20K100 for reformatting the data from all four slots
  • Altera 20K100 which implements integrated ODIN
Top view (large), Bottom view (large, small)
Detail of integrated ODIN output (large, small)

STATUS

Hardware

July 2000 First discussions about the active transition module
22 December 2000 Schematics design finished and reviewed. Still needs review from Altera application engineer and NIKHEF.
PCB design will start end of January 2001
22 February 2001 PCB design finished, final review still to be done.
5 March 2001 3 PCBs are ordered
5 April 2001 3 PCBs received. Will be sent for mounting of components on 19 April
29 May 2001 Mounted PCBs received. 

Software

22 December 2000 Altera VHDL skeleton written. Detailed implementation will be done by Tilecal
22 February 2001 Jose Castello passed at CERN to discuss Altera software needed.

DOCUMENTATION

CONTACTS

CERN - High Speed Interconnect - S-LINK
Erik van der Bij - 10 July 2001