VHDL models of S-LINK

DESCRIPTION

To help S-LINK designers in debugging their links designs or motherboard designs, an extensive set of VHDL models has been made.

FEMB Extensive model. Controlled by a text file. Outputs interpreted commands and timing in a text file. Extensive timing checks are performed

LSC Simple model using a parallel cable. Does not implement test mode

LDC Simple model using a parallel cable. Does not implement test mode

ROMB Extensive model. Controlled by a text file. Outputs interpreted commands and timing in a text file. Extensive timing checks are performed

STATUS

14 May 1996	The FEMB - ? - ROMB system is finished. It has been tested with dummy S-LINK - simply the connection between FEMB and ROMB, as it is suggested in the S-LINK Implementation Guide. Written by Piotr Kapusta.
16 May 2000	After four years, the model is revived in view of making a complete set of simulation models for helping debugging an ODIN VHDL core. Minimal modifications were required.

DOCUMENTATION

CERN EDMS system

Commands for driving the VHDL model of the FEMB
Commands for driving the VHDL model of the ROMB

CONTACTS

CERN - High Speed Interconnect - S-LINK
Erik van der Bij - 17 May 2000

FEMB	Extensive model. Controlled by a text file. Outputs interpreted commands and timing in a text file. Extensive timing checks are performed
LSC	Simple model using a parallel cable. Does not implement test mode
LDC	Simple model using a parallel cable. Does not implement test mode
ROMB	Extensive model. Controlled by a text file. Outputs interpreted commands and timing in a text file. Extensive timing checks are performed