The FEMB model will check if the signals from the LSC fullfil the timing requirements of the S-LINK specification. If a violation is detected, an assertion message is generated and the violation will be logged in the file "femb_out.txt".
<time> - VHDL-like format (space between number and unit !);<integer dec> - integer decimal number;<integer hex> - integer hex number;<edge> - one of the strings : "up", "down".<std_logic> - 0 or 1.
|
command
|
qualifier
|
parameter
|
operation
|
|---|---|---|---|
|
set
|
clkh
|
<time>
|
sets UCLK high time (default 12,5 ns)
|
|
set
|
clkl
|
<time>
|
sets UCLK low time (default 12,5 ns)
|
|
set
|
ds
|
<time>
|
sets data set-up time (default 10 ns)
|
|
set
|
dh
|
<time>
|
sets data hold time (default 1 ns)
|
|
set
|
es
|
<time>
|
sets UWEN# set-up time (default 10 ns)
|
|
set
|
eh
|
<time>
|
sets UWEN# hold time (default 1 ns)
|
|
set
|
wff
|
<time>
|
set max. allowed delay for LFF# low after CLK goes
high (default 12 ns)
|
|
set
|
ex
|
<integer dec>
|
sets number of extra words after LFF# goes low (default
2)
|
|
set
|
width
|
<integer dec>
|
sets data width used in model (8,16,32) (default
32)
|
|
set
|
dres
|
<integer dec>
|
sets number of idle UCLK cycles after URESET# goes
up (default 4)
|
|
set
|
pati
|
<integer hex>
|
sets initial value for pattern generation (default
0)
|
|
set
|
patt
|
<integer dec>
|
sets type of pattern used for data generation. Following
patterns cn be specified:
0 - walking "1";
<number> - next value:=previous value + <number>
(default 0)
|
|
command
|
qualifier
|
parameter
|
operation
|
|---|---|---|---|
|
reset
|
performs reset operation. Waits for LDOWN# down and
after for LDOWN# up.
|
||
|
start
|
clk
|
starts the clock. Do not start at time 0
|
|
|
send
|
data
|
<integer hex>
|
sends one data word respecting LFF#
|
|
send
|
bdata
|
<integer dec>
|
sends number of data words (pattern), respecting
LFF#
|
|
send
|
ctrl
|
<integer hex>
|
sends one control word , respecting LFF#
|
|
finish
|
terminates the simulation
|
|
command
|
qualifier
|
parameter
|
operation
|
|---|---|---|---|
|
wait
|
for
|
<time>
|
suspends stimulus changes for specified time
|
|
wait
|
clk
|
<edge>
|
suspends stimulus till the edge of the UCLK
|
|
wait
|
lff
|
<edge>
|
suspends stimulus till the edge of the LFF#
|
|
wait
|
ldown
|
<edge>
|
suspends stimulus till the edge of the LDOWN#
|
|
assert
|
utest
|
<std_logic>
|
sets level of the UTEST#
|
|
assert
|
ureset
|
<std_logic>
|
sets level of the URESET#
|
|
assert
|
uctrl
|
<std_logic>
|
sets level of the UCTRL#
|
|
assert
|
uwen
|
<std_logic>
|
sets level of the UWEN#
|
|
assert
|
ud
|
<integer hex>
|
sets level of the UD(31:0>
|