The ROMB model will check if the signals from the LDC fullfil the timing requirements of the S-LINK specification. If a violation is detected, an assertion message is generated and the violation will be logged in the file "romb_out.txt".
<time> - VHDL-like format (space between number and unit!);<integer dec> - integer decimal number;<integer hex> - integer hex number;<edge> - one of the strings : "up", "down".<std_logic> - 0 or 1.
command
|
qualifier
|
parameter
|
operation
|
---|---|---|---|
set
|
ds
|
<time>
|
sets data set-up time (default 10 ns)
|
set
|
dh
|
<time>
|
sets data hold time (default 1 ns)
|
set
|
es
|
<time>
|
sets LWEN# set-up time (default 10 ns)
|
set
|
eh
|
<time>
|
sets LWEN# hold time (default 1 ns)
|
set
|
width
|
<integer dec>
|
sets data width used in model (8,16,32) (default
32)
|
set
|
depth
|
<integer dec>
|
set FIFO warning level. When the FIFO contains more
words then "depth" the UXOFF# is asserted (default 4)
|
set
|
per
|
<time>
|
sets period between consecutive (multi-word) FIFO
reads (default 25 ns)
|
command
|
qualifier
|
parameter
|
operation
|
---|---|---|---|
reset
|
performs reset operation. Waits for LDOWN# down and
after for LDOWN# up. The FIFO is cleared.
|
||
take
|
data
|
<integer dec>
|
Reads number of words from the FIFO. The period between
reads is defined by "set per" command. If the FIFO becomes empty read time
is extended (until fresh data from the S-link will come).
|
put
|
url
|
<integer hex>
|
Sets state of URL lines. Only LSB nibble is valid.
|
finish
|
ends simulation
|
command
|
qualifier
|
parameter
|
operation
|
---|---|---|---|
wait
|
for
|
<time>
|
suspends stimulus changes for specified time
|
wait
|
clk
|
<edge>
|
suspends stimulus till the edge of the LCLK
|
wait
|
uxoff
|
<edge>
|
suspends stimulus till the edge of the UXOFF#
|
assert
|
utdo
|
<std_logic>
|
assert UTDO#
|
assert
|
ureset
|
<std_logic>
|
assert URESET#
|