Event-fragment data will be received on an S-LINK LDC interface connection from the ROD at an average rate of up to 100 MBytes/sec and written directly into "pages" of buffer memory using addresses taken from the "free-page FIFO". There will need to be some buffering between the S-LINK input and the buffer memory since each is driven by a different clock, but a long FIFO is not required. Indeed a simple "double-buffer" may suffice.

Under certain circumstances an XOFF signal back to the ROD will be generated on the S-LINK interface in order to stem the flow of data. This will automatically occur whenever the number of entries in the free-page FIFO drops below a programmable threshold, or when the ROB-IN is powered up or reset.

At the end of each page, or at the end of each event-fragment, the last address used will be written to the "used-page FIFO" along with status bits indicating whether this is the first, intermediate, or last page of the event-fragment. The address logic will then read the next value in the free-page FIFO as a base for addressing the subsequent page.

Both the START and the END of each event-fragment will be signalled on the S-LINK input (for instance by bits in a "control" word flagged by the S-LINK control/data bit). The length of pages will be adjustable in the hardware logic. Neither this nor the buffer-memory size should be unduly constrained by address-widths.

• 20 August 1997. A first version in PCI form-factor will be designed.
• 16 April 1998. Prototypes have been working with a limited amount of pages. A design review has been done at CERN on the design of a second version. This version will use a 3.3 Volt i960RD processor which runs at 66 MHz internally.
• 5 August 1998. New PCI version works fine now. Tested with 5 Volt i960RP version. One board delivered to DAQ Prototype-1. PMC version designed and sent for fabrication.
• 10 October 2000. A new version will be designed. It will use a faster i960 processor. Instead of MACH FPGA chips with a proprietary design language, Altera chips programmed with VHDL will be used. The board will have a double ODIN S-LINK LDC integrated and will not have an S-LINK connector. Prototypes expected by May 2001.

• ATLAS RoB-in project documentation
• RoB-in detailed design documentation
• The ATLAS ROB Complex working group

• Barry Green
• Bob Cranfield

CERN - High Speed Interconnect - S-LINK
Erik van der Bij - 10 October 2000