CERN is currently building a new accelerator to allow the study of collisions between elementary particles at very high energies. A major problem will be the huge amounts of data produced during a collision combined, with the frequency at which collisions occur. For example, the ATLAS[2] experiment requires a computer system to perform real-time analysis at the rate of 10 Gbytes/s on this data.
The use of high-performance commodity processors, like the DEC Alpha, Power PC, or Pentium, to perform the real-time analysis is interesting because of their very good price/performance ratio. Apart from computing power, high-performance communication between the computing nodes is also essential. In this context, a DS Network Interface Controller (DSNIC) has been developed. The DSNIC has allowed us to investigate building a parallel computer using high-throughput low-latency IEEE 1355 DS links[10] and 200 MHz Pentium Pro PCs running the Linux 2.0.27 Operating System (OS). Building a high-performance parallel computer means aiming at reliable low-latency high-throughput communication that generates little CPU load. In this paper we describe how the design and realisation of the DSNIC reflect the performance aim. This work has been carried out as part of the EU funded ARCHES Esprit project[1].