M. Boosten et al.A PCI based Network Controller for IEEE 1355 DS Links Architectures, Languages and PatternsP.H. Welch and A.W.P. Bakkers1998
P.D.V. van der Stok
CERN, The European Laboratory for Particle Physics, Geneva, Switzerland
Eindhoven University of Technology, Eindhoven, The Netherlands
CERN, 513-R060, CH-1211 Geneva 23, Switzerland, +41-22-767-8705, Marcel.Boosten@cern.ch
We have investigated the construction of a parallel computer using IEEE 1355 high-throughput low-latency DS link networks and high-performance commodity processors running a standard operating system. In this context a DS Network Interface Controller (DSNIC) has been developed. The board's hardware, controlled by FPGA firmware, together with host software, provides a CSP based message passing interface between standard OS processes. This paper describes how the design and realisation of the DSNIC reflect our aim: low-latency high-throughput inter-process communication. We show the benchmark results, their analysis, and suggest further performance gains that might be possible.