A block diagram of the firmware components is shown in Figure 5. Two main data flows can be recognised: data reception and data transmission.
Figure 5: Block diagram of the firmware.
Comin takes care of packet reception, it splits packet headers from packet data. The headers are sent to the headlenfifo, and the data is sent to the infifo. Apart from splitting, comin also counts the length of the packet, which is known as soon as the end-of-packet character has been received. This length is also sent to the headlenfifo. Data in the headlenfifo is delivered to an AMCC mailbox, which can generate an interrupt. On a header reception interrupt, the host CPU can determine destination address of the packet data and establish the receiving DMA, thereby avoiding memory-to-memory copying.
To avoid a store-and-forward mechanism, the receiving DMA must be established as soon as the header of the packet has been received. To set up a DMA, the length of the DMA transfer must be known beforehand. Therefore flush pads out each packet to the full packet size, even though less data is communicated over the DS link. DMAs can now be set up immediately on header reception, using the full packet size.
Comout takes care of sending data and acknowledge packets. If data is available in both the ackfifo and the outfifo, data in the ackfifo will be selected. This way, acknowledgements can bypass enqueued data packets.
In order to hide the reaction latency of the software driver, there
are FIFOs on both the receiving and the transmitting side. The
buffer size of 1 Kbyte was chosen because it fits well into
the internal resources of the Altera FPGA. A 1 Kbyte FIFO can
hide a reaction latency up to 100 
s, which should be
sufficient.
Mux multiplexes the AMCC to all the FIFOs so that interleaved transmission and reception is possible. Passthru provides access to the registers of the C101s. The registers of both C101s are accessible via register I/O. The firmware only supports one C101 efficiently, i.e., with a DMA driven interface.