next up previous
Next: The RCube 8-way HS-Link Up: HS-Link Devices Previous: HS-Link Devices

The Bullit HS-Link Interface Chip

The Bullit chip [3] provides a parallel interface to an HS-Link. Figure 2 shows the block diagram of the device. It consists of a transmitter/receiver pair, FIFO buffers and a low level protocol engine.

 
Figure 2: Block Diagram of the Bullit Chip  

The device has internal 80 character deep input and output FIFOs. The access to these FIFOs is by separate two byte wide parallel interfaces. The protocol engine implements the low-level link protocol and performs functions such as 8B/12B encoding/decoding, flow control to avoid receiver FIFO overrun, automatic insertion and deletion of IDLE characters and acknowledged link startup and shutdown. The HS-Link macrocell performs transmit clock frequency multiplication, character clock recovery and character serialisation and deserialisation. The speed of the transmitter section is controlled by a single byte rate clock.



Stefan Haas
Tue Mar 31 11:54:08 MET DST 1998