The RCube and Bullit chips are ``technology enabling'' devices designed to bring the advantages of low power, high speed serial technology to potential applications. To move from these devices to commercially successful implementations depends, among other things, on demonstrating that the technology meets the demands of all of the boundary conditions and how well it performs and scales under full-load conditions. To this end a large test and demonstration switching network of a minimum of 64 ports has been designed that not only will answer these questions but also provide a facility for exploiting the capacity of IEEE 1355 to successfully transport other protocols such as SCI, ATM and Ethernet.
Building on the experiences of the Macrame studies it was decided to base the switch architecture on the multistage Clos network topology while still allowing for the possibility of other topologies. The basic issue is one of packaging, e.g. how many router to router interconnects will be fixed on printed circuits and how many will be user configurable through cabled interconnects?
The choice was made to build a central switch Clos of 32 ports on one printed circuit module. Another module would be used to house four individual RCubes for which all the available links would be brought out to front panel cabling. An HS-Link traffic generator was designed to provide the switch with user controllable traffic patterns capable of operating at the link bandwidth. Therefore the testbed can be constructed from the following three basic modules:
Figure 5: HS-Link Network testbed Architecture