20 June 2002. You're an electronics engineer, are not afraid of crossing speed-limits of 2.5 gigabits per second and you like that many people use the stuff that you design? Words like VHDL, Altera, Serialisers, 8B10B coding, 64-bit/66MHz PCI, differential transmission lines, terminations and fibre-optic transceivers sound like fun to you?
We've just opened a post that may keep you busy in a successful project for at least three years. In the job description you can find all details about this position in the international working environment of CERN. Be fast to apply, halfway July is about the latest moment you can send in the application letter for the job you always have dreamt of.
Have a look at the S-LINK web pages to see what it's all about. Contact Robert McLaren or Erik van der Bij if you have any questions about this post.
20 June 2002. The first successful pulsar observation has been carried out in
January 2002, using the 32 meter dish Radiotelescope, at Medicina, Italy with the new
Pulsar Observation System.
The system uses the parallel electrical E-Slink from Nowoczesna Elektronika together with
an SSPCI board from Incaa Computers to transfer data from the
front-end data acquisition system to a Pentium III computer running Linux. A FEMB
board has been designed using an fpga XC4006 from xilinx, to host the LSC and to pack the
128 bit per sample data (extracted from digitizer) in 32 bit word to be transmitted to the
PC. The FEMB also produces the required sampling clock for the digitizer system synch with
UTC.
Each pulsar observation lasts from 20 minutes to a few hours, with a sustained data rate up to 1.3 MB/s. Thanks to the Linux driver sspci 1.0.1 from Sidik Isani of cfht, who implements an easy to use ring data buffer structure, a long observation (1.5GB to 20GB) with simultaneous data acquisition, time synch check and data storage on disk or dlt tape, has been achieved using a 32 MB memory buffer only. The driver needed a little modification to include the function required to check the ring buffer overwrite.
The transfer rate is negligible compared to the S-LINK performance, application, but the use of it has many advantages:
The acquisition system is now fully operational. More information on http://tucanae.bo.astro.it/pulsar/32mt/.
15 April 2002. It is likely that PCs will be used in the ATLAS Readout Buffer application. In this application high performance approaching the theoretical limit of the PCI bus is required. The performance will be limited either by using a very high data throughput, or by using a high frequency of small messages where the cycle overhead will limit the performance.
As a spin of from the S32PCI64 S-Link
interface we have developed a card to measure the burst performance of 64-bit PCI
systems. This card, called the PCI_BLASTER,
uses the same hardware as the S32PCI64 but has a different firmware loaded into the FPGA
designed by Wieslaw Iwanski from INP. This firmware and the associated Linux device driver
and user application written by Markus Joos from CERN allow a user to generate PCI
bursts in any of the types listed below:
| Memory Read Memory Read Line Memory Read Multiple |
Memory Write Memory Write and Invalidate |
Table: PCI cycle types supported by the PCI_BLASTER
The size of the bursts can be up to 64 MB. The built in timer of the PCI-BLASTER allows
to measure the time it takes to execute a block transfer of a given size and to calculate
the bandwidth in MB/s. A deeper analysis of the PCI bursts can be made with an additional
PCI analyser (available from the CERN Electronics Pool). Tests carried out so far have
shown that the PCI performance depends crucially on the type of host bridge and on the
type of PCI cycle used.
Preliminary measurements on different desktop PCs show bandwidth figures ranging from 28
(twenty eight) to 520 MB/s. Detailed results which are needed to evaluate the performance
of PCs in ATLAS Readout Buffer applications, will be published at a later moment.
The article "PCI, Efficient Use" from Frank Hady at Intel explains when each type of PCI cycle should be used and shows the definitions of PCI Utilization, Throughput and Efficiency.
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2 April 2002. The CMS HCAL
detector has successfully completed its source
calibration tests. The DAQ system uses S-LINK for data acquisition (DMA at 70-80
MBytes/s). The data was received using the Hawaii driver (a Linux driver for the S-LINK to PMC interface written by the CFHT Telescope team). The tests allowed a precision measurement (better than 1%) of the tiny source signal (0.086 least counts Poisson mean, least counts) on top of Gaussian noise (1.6 least counts, rms). Jim Rohlf from Boston University will write up the results for CMS HCAL publication in NIM. |
27 March 2002. The ATLAS experiment will use one standard link to move the data from all Read-out Drivers (RODs) from the subdetectors from the experiment 100 meter down under the ground to the Read-out Buffers (ROBs) located in buildings on the surface. Around 1500 of those links are needed, each one moving data at 160 MByte/s.
In December 2001 the ATLAS ROD Working Group Readout Link Task Force made recommendations concerning this link. Those recommendations were endorsed at the ATLAS Executive Board meeting on the 15th of February 2002:
The S-LINK team has taken up the responsibility for the recommendation that an S-LINK mezzanine card using 2.5 Gbps components and requiring only two fibres per Readout Link be designed.
On the web page of the ROD Working Group you can find a link to the Read-out Link section which contains hints and tips for ROD designers.
26 March 2002. The LHCb RICH detector uses the GOL serialiser chip developed by the CERN MIC group as data transmitter. Currently the data from this chip will be read out over a modified ODIN LDC as that one contains all that is needed to receive the G-LINK compatible data. Gillian Damerell, who formerly was at CERN and had developed specific ATLAS code for the SLIDAS data generator, is modifying the ODIN Altera firmware to make it work with the data sent by the RICH detector. John Bibby from the University of Oxford is leading this effort.
| 5 February 2002. The 32-bit S-LINK to 64-bit PCI
interface (S32PCI64) designed by Wieslaw Iwanski from the Polish Institute for Nuclear
Physics can move data from a 32-bit S-LINK Link Destination Card to any 32-bit or 64-bit
PCI bus that runs at 33 MHz. It is a high-speed follow up of the Simple S-LINK to PCI interface. The S32PCI64 will have a lower PCI-bus utilization and needs much less host processor control. The source code of the Linux user library for this interface is only 10 KByte in size, showing that the interface is easy to program. Three prototypes have been built. Transfer rates to host memory of over 150 MB/s with one interface and 300 MB/s with two interfaces on a single 64-bit/66MHz PCI bus segment have been shown. The required software overhead per block transfer is only in the order of 2.5 us. The company Nowoczesna Elektronika manufactures and sells the S32PCI64. Note: the S32PCI64 only works in 3.3 Volt PCI slots and is only able to accept 3.3 Volt Link Destination Cards. |
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CERN - High Speed Interconnect - S-LINK
Erik van der Bij - 20 June 2002