4.0 S-LINK Usage Instructions
Four lines are provided to allow the ROMB to send signals back to the FEMB. The lines URL[3..0] are inputs to the LDC. The LSC has output lines LRL[3..0] which reflect the state of URL[3..0]. The lines are updated frequently but there is no guaranteed delivery time nor is it guaranteed that the lines will be updated synchronously.
If a pulse is to be sent on these lines, the minimum pulse duration on URL[3..0] shall be 32 clock cycles of LCLK. The minimum pulse duration delivered on LRL[3..0] shall be 16 clock cycles of LCLK.
In this way, the lines have the appearance of four wires running back from the LDC to the LSC. They are intended for applying level-sensitive signals and slow control pulses to the FEMB and not for fast data transmission.
There is no equivalent of LDERR# on the return lines. Data words transmitted back to the LSC are checked for transmission errors but if an error is detected, the LSC simply does not update LRL[3..0]. If the error is a transient one, the lines will be updated on the next cycle. If the error is more serious and would prevent the minimum pulse of 16 clock cycles being transmitted, the LSC will set LDOWN# low.
The return lines continue to function during test mode (see Section 4.9). During a reset cycle (see Section 4.11), the return lines are set low and are updated as soon as possible after reset.
Note that if a FEMB or ROMB is to be constructed for a simplex S-LINK, these lines shall be connected to GND on the ROMB and left unconnected on the FEMB. In this way, the FEMB and ROMB will still work with a duplex S-LINK. In the case of a simplex S-LINK, the lines URL[3..0] on the LDC shall be left unconnected and the lines LRL[3..0] on the LSC shall be connected to GND.