Application of T9000 to CPLEAR

7 Communication Measurements

The time between the sending of a short packet and the reception of an acknowledge packet between two directly connected T9000s was measured to be 7.5 msecs. The additional delay incurred by connecting two T9000s via a C104 was measured to be 1 msec (see Fig. ). The curve intercepts the y-axis at 2 msec which represents the time between the sending of a data packet and the reception of the acknowledge packet, i.e. the extra delay in transmitting two packets.

In Fig. 13 the dependency of the bandwidth on the number of virtual links used is demonstrated. The figure shows the bandwidth as a function of message size for one to five virtual links mapped onto a single physical link. The bandwidth represents the usable amount of data exchanged between two T9000s running at 20 MHz. The increase in bandwidth can be accounted for by the increased packet inter-leaving performed by the VCP and more efficient use of its pipelined architecture. When multiple virtual links are used, packets for different virtual links may be transmitted independently of the reception of acknowledge packets on other virtual links.

The measured bandwidths as a function of message size when using 20 and 25 MHz processors are shown in Figs. and . In these measurements the links are routed through different C104s, i.e. the curve for four links uses four independent C104s. This configuration is dictated by the architecture of the GPMIMD motherboards. The theoretical limit for the bandwidth is 9.5 Mbytes/s on each physical link. The bandwidths measured at 20 and 25 MHz fall short of this, but there is a clear improvement from the 20-to-25 MHz processors. The problem is believed to be due to the inability of the VCP, at 20 MHz, to fully exploit the capacity of the links. If the T9000 were running at 30 MHz the VCP should be able to reach the theoretical limits for the link bandwidth.

Application of T9000 to CPLEAR - 09 NOV 95

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